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            <div class="title">SDIO - SDIO Control Registers</div>
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        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 class="panel-title"> SDIO Register Index</h3>
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            <div class="panel-body">
                <table>
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000000:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#SDMA" target="_self">SDMA - SDMA system address</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000004:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#BLOCK" target="_self">BLOCK - Block size</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000008:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#ARGUMENT1" target="_self">ARGUMENT1 - Argument1</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x0000000C:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#TRANSFER" target="_self">TRANSFER - Transfer mode</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000010:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#RESPONSE0" target="_self">RESPONSE0 - Response0</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000014:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#RESPONSE1" target="_self">RESPONSE1 - Response1</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000018:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#RESPONSE2" target="_self">RESPONSE2 - Response2</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x0000001C:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#RESPONSE3" target="_self">RESPONSE3 - Response3</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000020:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#BUFFER" target="_self">BUFFER - Buffer data port</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000024:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#PRESENT" target="_self">PRESENT - Present state</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000028:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#HOSTCTRL1" target="_self">HOSTCTRL1 - Host control 1</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x0000002C:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#CLOCKCTRL" target="_self">CLOCKCTRL - Clock control</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000030:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#INTSTAT" target="_self">INTSTAT - Interrupt enable</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000034:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#INTENABLE" target="_self">INTENABLE - Normal interrupt status enable</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000038:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#INTSIG" target="_self">INTSIG - Normal interrupt signal enable</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x0000003C:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#AUTO" target="_self">AUTO - Auto CMD error status</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000040:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#CAPABILITIES0" target="_self">CAPABILITIES0 - Capabilities</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000044:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#CAPABILITIES1" target="_self">CAPABILITIES1 - Capabilities</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000048:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#MAXIMUM0" target="_self">MAXIMUM0 - Maximum current capabilities</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x0000004C:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#MAXIMUM1" target="_self">MAXIMUM1 - Maximum current capabilities</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000050:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#FORCE" target="_self">FORCE - Force event register for error interrupt status</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000054:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#ADMA" target="_self">ADMA - ADMA error status</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000058:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#ADMALOWD" target="_self">ADMALOWD - ADMA system address [31:0]</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x0000005C:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#ADMAHIWD" target="_self">ADMAHIWD - ADMA system address [63:0]</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000060:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#PRESET0" target="_self">PRESET0 - Preset Value initialization and default speed</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000064:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#PRESET1" target="_self">PRESET1 - Preset Value for high speed and SDR12</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000068:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#PRESET2" target="_self">PRESET2 - Preset Value for SDR25 and SDR50</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x0000006C:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#PRESET3" target="_self">PRESET3 - Preset Value for SDR104 and DDR50</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000070:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#BOOTTOCTRL" target="_self">BOOTTOCTRL - Boot Data Timeout control</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000078:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#VENDOR" target="_self">VENDOR - Vendor</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x000000FC:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#SLOTSTAT" target="_self">SLOTSTAT - Slot interrupt status</a>
                        </td>
                    </tr>

                </table>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="SDMA" class="panel-title">SDMA - SDMA system address</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40070000</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>SDMA system address</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="32">SDMASYSTEMADDRESS
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:0</td>
                            <td>SDMASYSTEMADDRESS</td>
                            <td>RW</td>
                            <td>This register contains the physical system memory address used for DMA transfers or the second argument for the Auto CMD23. (1) SDMA System Address This register contains the system memory address for a SDMA transfer. When the Host Controller stops a SDMA transfer, this register shall point to the system address of the next contiguous data position. It can be accessed only if no transaction is executing (i.e., after a transaction has stopped). Read operations during transfers may return an invalid value. The Host Driver shall initialize this register before starting a SDMA transaction. After SDMA has stopped, the next system address of the next contiguous data position can be read from this register. The SDMA transfer waits at the every boundary specified by the Host SDMA Buffer Boundary in the Block Size register. The Host Controller generates DMA Interrupt to request the Host Driver to update this register. The Host Driver sets the next system address of the next data position to this register. When the most upper byte of this register (003h) is written, the Host Controller restarts the SDMA transfer. When restarting SDMA by the Resume command or by setting Continue Request in the Block Gap Control register, the Host Controller shall start at the next contiguous address stored here in the SDMA System Address register. ADMA does not use this register (2) Argument 2 This register is used with the Auto CMD23 to set a 32-bit block count value to the argument of the CMD23 while executing Auto CMD23. If Auto CMD23 is used with ADMA, the full 32-bit block count value can be used. If Auto CMD23 is used without AMDA, the available block count value is limited by the Block Count register. 65535 blocks is the maximum value in this case.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="BLOCK" class="panel-title">BLOCK - Block size</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40070004</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Block size</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="16">BLKCNT
                                <br>0x0</td>

                            <td align="center" colspan="1">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="3">HOSTSDMABUFSZ
                                <br>0x0</td>

                            <td align="center" colspan="12">TRANSFERBLOCKSIZE
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:16</td>
                            <td>BLKCNT</td>
                            <td>RW</td>
                            <td>This register is enabled when Block Count Enable in the Transfer Mode register is set to 1 and is valid only for multiple block transfers. The HC decrements the block count after each block transfer and stops when the count reaches zero. It can be accessed only if no transaction is executing (i.e. after a transaction has stopped). Read operations during transfer return an invalid value and write operations shall be ignored. When saving transfer context as a result of Suspend command, the number of blocks yet to be transferred can be determined by reading this register. When restoring transfer context prior to issuing a Resume command, the HD shall restore the previously save block count.<br><br>
                                 STOPCNT              = 0x0 - Stop Count<br>
                             1BLOCK               = 0x1 - 1 block<br>
                             2BLOCKS              = 0x2 - 2 blocks (and so on from 1-65535)<br>
                             65535BLOCKS          = 0xFFFF - 65535 blocks</td>
                        </tr>

                        <tr>
                            <td>15</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>14:12</td>
                            <td>HOSTSDMABUFSZ</td>
                            <td>RW</td>
                            <td>To perform long DMA transfer, System Address register shall be updated at every system boundary during DMA transfer. These bits specify the size of contiguous buffer in the system memory. The DMA transfer shall wait at the every boundary specified by these fields and the HC generates the DMA Interrupt to request the HD to update the System Address register. These bits shall support when the DMA Support in the Capabilities register is set to 1 and this function is active when the DMA Enable in the Transfer Mode register is set to 1.<br><br>
                                 4KB                  = 0x0 - 4KB(Detects A11 Carry out)<br>
                             8KB                  = 0x1 - 8KB(Detects A12 Carry out)<br>
                             16KB                 = 0x2 - 16KB(Detects A13 Carry out)<br>
                             32KB                 = 0x3 - 32KB(Detects A14 Carry out)<br>
                             64KB                 = 0x4 - 64KB(Detects A15 Carry out)<br>
                             128KB                = 0x5 - 128KB(Detects A16 Carry out)<br>
                             256KB                = 0x6 - 256KB(Detects A17 Carry out)<br>
                             512KB                = 0x7 - 512KB(Detects A18 Carry out)</td>
                        </tr>

                        <tr>
                            <td>11:0</td>
                            <td>TRANSFERBLOCKSIZE</td>
                            <td>RW</td>
                            <td>This register specifies the block size for block data transfers for CMD17, CMD18, CMD24, CMD25, and CMD53. It can be accessed only if no transaction is executing (i.e after a transaction has stopped). Read operations during transfer return an invalid value and write operations shall be ignored.<br><br>
                                 NODATAXFER           = 0x0 - No Data Transfer<br>
                             1BYTE                = 0x1 - 1 Byte<br>
                             2BYTES               = 0x2 - 2 Bytes<br>
                             3BYTES               = 0x3 - 3 Bytes<br>
                             4BYTES               = 0x4 - 4 Bytes (and so on from 1-2048)<br>
                             511BYTES             = 0x1FF - 511 Bytes<br>
                             512BYTES             = 0x200 - 512 Bytes<br>
                             2048BYTES            = 0x800 - 2048 Bytes</td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="ARGUMENT1" class="panel-title">ARGUMENT1 - Argument1</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40070008</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Argument1</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="32">CMDARG1
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:0</td>
                            <td>CMDARG1</td>
                            <td>RW</td>
                            <td>The SD Command Argument is specified as bit39-8 of Command-Format.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="TRANSFER" class="panel-title">TRANSFER - Transfer mode</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x4007000C</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Transfer mode</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="2">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="6">CMDIDX
                                <br>0x0</td>

                            <td align="center" colspan="2">CMDTYPE
                                <br>0x0</td>

                            <td align="center" colspan="1">DATAPRSNTSEL
                                <br>0x0</td>

                            <td align="center" colspan="1">CMDIDXCHKEN
                                <br>0x0</td>

                            <td align="center" colspan="1">CMDCRCCHKEN
                                <br>0x0</td>

                            <td align="center" colspan="1">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="2">RESPTYPESEL
                                <br>0x0</td>

                            <td align="center" colspan="10">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">BLKSEL
                                <br>0x0</td>

                            <td align="center" colspan="1">DXFERDIRSEL
                                <br>0x0</td>

                            <td align="center" colspan="2">ACMDEN
                                <br>0x0</td>

                            <td align="center" colspan="1">BLKCNTEN
                                <br>0x0</td>

                            <td align="center" colspan="1">DMAEN
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:30</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>29:24</td>
                            <td>CMDIDX</td>
                            <td>RW</td>
                            <td>This bit shall be set to the command number (CMD0-63, ACMD063).<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>23:22</td>
                            <td>CMDTYPE</td>
                            <td>RW</td>
                            <td>There are three types of special commands. Suspend, Resume and Abort. These bits shall bet set to 00b for all other commands. Suspend Command If the Suspend command succeeds, the HC shall assume the SD Bus has been released and that it is possible to issue the next command which uses the DAT line. The HC shall de-assert Read Wait for read transactions and stop checking busy for write transactions. The Interrupt cycle shall start, in 4-bit mode. If the Suspend command fails, the HC shall maintain its current state. and the HD shall restart the transfer by setting Continue Request in the Block Gap Control Register. Resume Command The HD re-starts the data transfer by restoring the registers in the range of 000-00Dh. The HC shall check for busy before starting write transfers. Abort Command If this command is set when executing a read transfer, the HC shall stop reads to the buffer. If this command is set when executing a write transfer, the HC shall stop driving the DAT line. After issuing the Abort command, the HD should issue a software reset<br><br>
                                 NORMAL               = 0x0 - Normal<br>
                             SUSPEND              = 0x1 - Suspend<br>
                             RESUME               = 0x2 - Resume<br>
                             ABORT                = 0x3 - Abort</td>
                        </tr>

                        <tr>
                            <td>21</td>
                            <td>DATAPRSNTSEL</td>
                            <td>RW</td>
                            <td>This bit is set to 1 to indicate that data is present and shall be transferred using the DAT line. If is set to 0 for the following: 1. Commands using only CMD line (ex. CMD52) 2. Commands with no data transfer but using busy signal on DAT[0] line (R1b or R5b ex. CMD38) 3. Resume Command<br><br>
                                 NODATAPRESENT        = 0x0 - No Data Present<br>
                             DATAPRESENT          = 0x1 - Data Present</td>
                        </tr>

                        <tr>
                            <td>20</td>
                            <td>CMDIDXCHKEN</td>
                            <td>RW</td>
                            <td>If this bit is set to 1, the HC shall check the index field in the response to see if it has the same value as the command index. If it is not, it is reported as a Command Index Error. If this bit is set to 0, the Index field is not checked.<br><br>
                                 DISABLE              = 0x0 - Disable<br>
                             ENABLE               = 0x1 - Enable</td>
                        </tr>

                        <tr>
                            <td>19</td>
                            <td>CMDCRCCHKEN</td>
                            <td>RW</td>
                            <td>If this bit is set to 1, the HC shall check the CRC field in the response. If an error is detected, it is reported as a Command CRC Error. If this bit is set to 0, the CRC field is not checked.<br><br>
                                 DISABLE              = 0x0 - Disable<br>
                             ENABLE               = 0x1 - Enable</td>
                        </tr>

                        <tr>
                            <td>18</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>17:16</td>
                            <td>RESPTYPESEL</td>
                            <td>RW</td>
                            <td>Response Type Select<br><br>
                                 NORESPONSE           = 0x0 - No Response<br>
                             LEN136               = 0x1 - Response length 136<br>
                             LEN48                = 0x2 - Response length 48<br>
                             LEN48CHKBUSY         = 0x3 - Response length 48 check Busy after response</td>
                        </tr>

                        <tr>
                            <td>15:6</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>5</td>
                            <td>BLKSEL</td>
                            <td>RW</td>
                            <td>This bit enables multiple block data transfers.<br><br>
                                 SINGLEBLOCK          = 0x0 - Single Block<br>
                             MULTIPLEBLOCK        = 0x1 - Multiple Block</td>
                        </tr>

                        <tr>
                            <td>4</td>
                            <td>DXFERDIRSEL</td>
                            <td>RW</td>
                            <td>Data Transfer Direction Select. This bit defines the direction of data transfers.<br><br>
                                 WRITE                = 0x0 - Write (Host to Card)<br>
                             READ                 = 0x1 - Read (Card to Host)</td>
                        </tr>

                        <tr>
                            <td>3:2</td>
                            <td>ACMDEN</td>
                            <td>RW</td>
                            <td>This field determines use of auto command functions. There are two methods to stop Multiple-block read and write operation. (1) Auto CMD12 Enable Multiple-block read and write commands for memory require CMD12 to stop the operation. When this field is set to 01b, the Host Controller issues CMD12 automatically when last block transfer is completed. Auto CMD12 error is indicated to the Auto CMD Error Status register. The Host Driver shall not set this bit if the command does not require CMD12. (2) Auto CMD23 Enable When this bit field is set to 10b, the Host Controller issues a CMD23 automatically before issuing a command specified in the Command Register The following conditions are required to use the Auto CMD23.<br><br>
                                 DISABLED             = 0x0 - Auto Command Disabled<br>
                             CMD12ENABLE          = 0x1 - Auto CMD12 Enable<br>
                             CMD23ENABLE          = 0x2 - Auto CMD23 Enable<br>
                             RSVD                 = 0x3 - This value is reserved.</td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>BLKCNTEN</td>
                            <td>RW</td>
                            <td>This bit is used to enable the Block count register, which is only relevant for multiple block transfers. When this bit is 0, the Block Count register is disabled, which is useful in executing an infinite transfer.<br><br>
                                 DISABLE              = 0x0 - Disable<br>
                             ENABLE               = 0x1 - Enable</td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>DMAEN</td>
                            <td>RW</td>
                            <td>DMA can be enabled only if DMA Support bit in the Capabilities register is set. If this bit is set to 1, a DMA operation shall begin when the HD writes to the upper byte of Command register (00Fh).<br><br>
                                 DISABLE              = 0x0 - Disable<br>
                             ENABLE               = 0x1 - Enable</td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="RESPONSE0" class="panel-title">RESPONSE0 - Response0</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40070010</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Response0</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="32">CMDRESP0
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:0</td>
                            <td>CMDRESP0</td>
                            <td>ROC</td>
                            <td>R[] refers to a bit range within the response data as transmitted on the SD Bus, REP[] refers to a bit range within the Response register.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="RESPONSE1" class="panel-title">RESPONSE1 - Response1</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40070014</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Response1</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="32">CMDRESP1
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:0</td>
                            <td>CMDRESP1</td>
                            <td>ROC</td>
                            <td>R[] refers to a bit range within the response data as transmitted on the SD Bus, REP[] refers to a bit range within the Response register.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="RESPONSE2" class="panel-title">RESPONSE2 - Response2</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40070018</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Response2</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="32">CMDRESP2
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:0</td>
                            <td>CMDRESP2</td>
                            <td>ROC</td>
                            <td>R[] refers to a bit range within the response data as transmitted on the SD Bus, REP[] refers to a bit range within the Response register.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="RESPONSE3" class="panel-title">RESPONSE3 - Response3</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x4007001C</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Response3</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="32">CMDRESP3
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:0</td>
                            <td>CMDRESP3</td>
                            <td>ROC</td>
                            <td>R[] refers to a bit range within the response data as transmitted on the SD Bus, REP[] refers to a bit range within the Response register.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="BUFFER" class="panel-title">BUFFER - Buffer data port</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40070020</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Buffer data port</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="32">BUFFERDATA
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:0</td>
                            <td>BUFFERDATA</td>
                            <td>RW</td>
                            <td>The Host Controller Buffer can be accessed through this 32-bit Data Port Register.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="PRESENT" class="panel-title">PRESENT - Present state</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40070024</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Present state</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="3">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="4">DAT74LINE
                                <br>0xf</td>

                            <td align="center" colspan="1">CMDLINE
                                <br>0x1</td>

                            <td align="center" colspan="4">DAT30LINE
                                <br>0xf</td>

                            <td align="center" colspan="1">WRPROTSW
                                <br>0x0</td>

                            <td align="center" colspan="1">CARDDET
                                <br>0x0</td>

                            <td align="center" colspan="1">CARDSTABLE
                                <br>0x0</td>

                            <td align="center" colspan="1">CARDINSERTED
                                <br>0x0</td>

                            <td align="center" colspan="4">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">BUFRDEN
                                <br>0x0</td>

                            <td align="center" colspan="1">BUFWREN
                                <br>0x0</td>

                            <td align="center" colspan="1">RDXFERACT
                                <br>0x0</td>

                            <td align="center" colspan="1">WRXFERACT
                                <br>0x0</td>

                            <td align="center" colspan="4">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">RETUNINGREQUEST
                                <br>0x0</td>

                            <td align="center" colspan="1">DLINEACT
                                <br>0x0</td>

                            <td align="center" colspan="1">CMDINHDAT
                                <br>0x0</td>

                            <td align="center" colspan="1">CMDINHCMD
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:29</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>28:25</td>
                            <td>DAT74LINE</td>
                            <td>RO</td>
                            <td>This status is used to check DAT line level to recover from errors, and for debugging.<br><br>
                                 DAT7                 = 0x8 - DAT[7]<br>
                             DAT6                 = 0x4 - DAT[6]<br>
                             DAT5                 = 0x2 - DAT[5]<br>
                             DAT4                 = 0x1 - DAT[4]</td>
                        </tr>

                        <tr>
                            <td>24</td>
                            <td>CMDLINE</td>
                            <td>RO</td>
                            <td>This status is used to check CMD line level to recover from errors, and for debugging.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>23:20</td>
                            <td>DAT30LINE</td>
                            <td>RO</td>
                            <td>This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[0].<br><br>
                                 DAT3                 = 0x8 - DAT[3]<br>
                             DAT2                 = 0x4 - DAT[2]<br>
                             DAT1                 = 0x2 - DAT[1]<br>
                             DAT0                 = 0x1 - DAT[0]</td>
                        </tr>

                        <tr>
                            <td>19</td>
                            <td>WRPROTSW</td>
                            <td>RO</td>
                            <td>The Write Protect Switch is supported for memory and combo cards. This bit reflects the SDWP# pin.<br><br>
                                 WRITEPROTECTED       = 0x0 - Write protected (SDWP# = 0)<br>
                             WRITEENABLED         = 0x1 - Write enabled (SDWP# = 1)</td>
                        </tr>

                        <tr>
                            <td>18</td>
                            <td>CARDDET</td>
                            <td>RO</td>
                            <td>This bit reflects the inverse value of the SDCD# pin.<br><br>
                                 NOCARDPRESENT        = 0x0 - No Card present (SDCD# = 1)<br>
                             CARDPRESENT          = 0x1 - Card present (SDCD# = 0)</td>
                        </tr>

                        <tr>
                            <td>17</td>
                            <td>CARDSTABLE</td>
                            <td>RO</td>
                            <td>This bit is used for testing. If it is 0, the Card Detect Pin Level is not stable. If this bit is set to 1, it means the Card Detect Pin Level is stable. The Software Reset For All in the Software Reset Register shall not affect this bit.<br><br>
                                 RESET_DEBOUNCING_NOCARD = 0x0 - Reset or Debouncing or No Card<br>
                             CARDINSERTED         = 0x1 - Card Inserted</td>
                        </tr>

                        <tr>
                            <td>16</td>
                            <td>CARDINSERTED</td>
                            <td>RO</td>
                            <td>This bit indicates whether a card has been inserted. Changing from 0 to 1 generates a Card Insertion interrupt in the Normal Interrupt Status register and changing from 1 to 0 generates a Card Removal Interrupt in the Normal Interrupt Status register. The Software Reset For All in the Software Reset register shall not affect this bit. If a Card is removed while its power is on and its clock is oscillating, the HC shall clear SD Bus Power in the Power Control register and SD Clock Enable in the Clock control register. In addition the HD should clear the HC by the Software Reset For All in Software register. The card detect is active regardless of the SD Bus Power.<br><br>
                                 RESET_DEBOUNCING_NOCARD = 0x0 - Reset or Debouncing or No Card<br>
                             CARDINSERTED         = 0x1 - Card Inserted</td>
                        </tr>

                        <tr>
                            <td>15:12</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>11</td>
                            <td>BUFRDEN</td>
                            <td>ROC</td>
                            <td>This status is used for non-DMA read transfers. This read only flag indicates that valid data exists in the host side buffer status. If this bit is 1, readable data exists in the buffer. A change of this bit from 1 to 0 occurs when all the block data is read from the buffer. A change of this bit from 0 to 1 occurs when all the block data is ready in the buffer and generates the Buffer Read Ready Interrupt.<br><br>
                                 DISABLE              = 0x0 - Read Disable<br>
                             ENABLE               = 0x1 - Read Enable.</td>
                        </tr>

                        <tr>
                            <td>10</td>
                            <td>BUFWREN</td>
                            <td>ROC</td>
                            <td>This status is used for non-DMA write transfers. This read only flag indicates if space is available for write data. If this bit is 1, data can be written to the buffer. A change of this bit from 1 to 0 occurs when all the block data is written to the buffer. A change of this bit from 0 to 1 occurs when top of block data can be written to the buffer and generates the Buffer Write Ready Interrupt.<br><br>
                                 DISABLE              = 0x0 - Write Disable<br>
                             ENABLE               = 0x1 - Write Enable.</td>
                        </tr>

                        <tr>
                            <td>9</td>
                            <td>RDXFERACT</td>
                            <td>ROC</td>
                            <td>This status is used for detecting completion of a read transfer. This bit is set to 1 for either of the following conditions: After the end bit of the read command When writing a 1 to continue Request in the Block Gap Control register to restart a read transfer This bit is cleared to 0 for either of the following conditions: When the last data block as specified by block length is transferred to the system. When all valid data blocks have been transferred to the system and no current block transfers are being sent as a result of the Stop At Block Gap Request set to 1. A transfer complete interrupt is generated when this bit changes to 0.<br><br>
                                 TRANSFERRING         = 0x1 - Transferring data<br>
                             NOVALIDATA           = 0x0 - No valid data</td>
                        </tr>

                        <tr>
                            <td>8</td>
                            <td>WRXFERACT</td>
                            <td>ROC</td>
                            <td>This status indicates a write transfer is active. If this bit is 0, it means no valid write data exists in the HC. This bit is set in either of the following cases: After the end bit of the write command. When writing a 1 to Continue Request in the Block Gap Control register to restart a write transfer. This bit is cleared in either of the following cases: After getting the CRC status of the last data block as specified by the transfer count (Single or Multiple) After getting a CRC status of any block where data transmission is about to be stopped by a Stop At Block Gap Request. During a write transaction, a Block Gap Event interrupt is generated when this bit is changed to 0, as a result of the Stop At Block Gap Request being set. This status is useful for the HD in determining when to issue commands during write busy.<br><br>
                                 TRANSFERRING         = 0x1 - transferring data<br>
                             NOVALIDDATA          = 0x0 - No valid data</td>
                        </tr>

                        <tr>
                            <td>7:4</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>3</td>
                            <td>RETUNINGREQUEST</td>
                            <td>RO</td>
                            <td>Re-Tuning Request Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive correct data. This bit is cleared when a command is issued with setting Execute Tuning in the Host Control 2 register. Changing of this bit from 0 to 1 generates Re-Tuning Event. Refer to Normal Interrupt registers for more detail. This bit isn't set to 1 if Sampling Clock Select in the Host Control 2 register is set to 0 (using fixed sampling clock).<br><br>
                                 RETUNENEEDED         = 0x1 - Sampling clock needs re-tuning<br>
                             WELLTUNED            = 0x0 - Fixed or well tuned sampling clock</td>
                        </tr>

                        <tr>
                            <td>2</td>
                            <td>DLINEACT</td>
                            <td>ROC</td>
                            <td>This bit indicates whether one of the DAT line on SD bus is in use.<br><br>
                                 ACTIVE               = 0x1 - DAT line active<br>
                             INACTIVE             = 0x0 - DAT line inactive</td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>CMDINHDAT</td>
                            <td>ROC</td>
                            <td>This status bit is generated if either the DAT Line Active or the Read transfer Active is set to 1. If this bit is 0, it indicates the HC can issue the next SD command. Commands with busy signal belong to Command Inhibit (DAT) (ex. R1b, R5b type). Changing from 1 to 0 generates a Transfer Complete interrupt in the Normal interrupt status register. Note: The SD Host Driver can save registers in the range of 000-00Dh for a suspend transaction after this bit has changed from 1 to 0.<br><br>
                                 DONTISSUE            = 0x1 - cannot issue command which uses the DAT line<br>
                             ISSUE                = 0x0 - Can issue command which uses the DAT line</td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>CMDINHCMD</td>
                            <td>ROC</td>
                            <td>If this bit is 0, it indicates the CMD line is not in use and the HC can issue a SD command using the CMD line. This bit is set immediately after the Command register (00Fh) is written. This bit is cleared when the command response is received. Even if the Command Inhibit (DAT) is set to 1, Commands using only the CMD line can be issued if this bit is 0. Changing from 1 to 0 generates a Command complete interrupt in the Normal Interrupt Status register. If the HC cannot issue the command because of a command conflict error or because of Command Not Issued By Auto CMD12 Error, this bit shall remain 1 and the Command Complete is not set. Status issuing Auto CMD12 is not read from this bit. Auto CMD12 and Auto CMD23 consist of two responses. In this case, this bit is not cleared by the response of CMD12 or CMD23 but cleared by the response of a read/write command. Status issuing Auto CMD12 is not read from this bit. So if a command is issued during Auto CMD12 operation, Host Controller shall manage to issue two commands: CMD12 and a command set by Command register. Note: DAT line active indicates whether one of the DAT line is on SD bus is in use. (a) In the case of read transactions This status indicates whether a read transfer is executing on the SD Bus. Changing this value from 1 to 0 generates a Block Gap Event interrupt in the Normal Interrupt Status register, as the result of the Stop At Block Gap Request being set. This bit shall be set in either of the following cases: (1) After the end bit of the read command. (2) When writing a 1 to Continue Request in the Block Gap Control register to restart a read transfer. This bit shall be cleared in either of the following cases: (1) When the end bit of the last data block is sent from the SD Bus to the Host Controller. In case of ADMA2, the last block is designated by the last transfer of Descriptor Table. (2) When a read transfer is stopped at the block gap initiated by a Stop At Block Gap Request. The Host Controller shall stop read operation at the start of the interrupt cycle of the next block gap by driving Read Wait or stopping SD clock. If the Read Wait signal is already driven (due to data buffer cannot receive data), the Host Controller can continue to stop read operation by driving the Read Wait signal. It is necessary to support Read Wait in order to use suspend / resume function. (b) In the case of write transactions This status indicates that a write transfer is executing on the SD Bus. Changing this value from 1 to 0 generate a Transfer Complete interrupt in the Normal Interrupt Status register. This bit shall be set in either of the following cases: (1) After the end bit of the write command. (2) When writing to 1 to Continue Request in the Block Gap Control register to continue a write transfer. This bit shall be cleared in either of the following cases: (1) When the SD card releases write busy of the last data block. If SD card does not drive busy signal for 8 SD Clocks, the Host Controller shall consider the card drive Not Busy. In case of ADMA2, the last block is designated by the last transfer of Descriptor Table. (2) When the SD card releases write busy prior to waiting for write transfer as a result of a Stop At Block Gap Request. (c) Command with busy This status indicates whether a command indicates busy (ex. erase command for memory) is executing on the SD Bus. This bit is set after the end bit of the command with busy and cleared when busy is de-asserted. Changing this bit from 1 to 0 generate a Transfer Complete interrupt in the Normal Interrupt Status register. Note: The HD can issue cmd0, cmd12, cmd13 (for memory) and cmd52 (for SDIO) when the DAT lines are busy during data transfer. These commands can be issued when Command Inhibit (CMD) is set to zero. Other commands shall be issued when Command Inhibit (DAT) is set to zero.<br><br>
                                 DONTISSUE            = 0x1 - CMD line is in use<br>
                             ISSUE                = 0x0 - Indicates that the CMD line is not in use and the HC can issue a SD command using the CMD line.</td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="HOSTCTRL1" class="panel-title">HOSTCTRL1 - Host control 1</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40070028</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Host control 1</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="5">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">WUENCARDREMOVL
                                <br>0x0</td>

                            <td align="center" colspan="1">WUENCARDINSERT
                                <br>0x0</td>

                            <td align="center" colspan="1">WUENCARDINT
                                <br>0x0</td>

                            <td align="center" colspan="1">BOOTACKCHK
                                <br>0x1</td>

                            <td align="center" colspan="1">ALTBOOTEN
                                <br>0x0</td>

                            <td align="center" colspan="1">BOOTEN
                                <br>0x0</td>

                            <td align="center" colspan="1">SPIMODE
                                <br>0x0</td>

                            <td align="center" colspan="1">GAP
                                <br>0x0</td>

                            <td align="center" colspan="1">READWAITCTRL
                                <br>0x0</td>

                            <td align="center" colspan="1">CONTREQ
                                <br>0x0</td>

                            <td align="center" colspan="1">STOPATBLOCKGAPREQUEST
                                <br>0x0</td>

                            <td align="center" colspan="3">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">HWRESET
                                <br>0x0</td>

                            <td align="center" colspan="3">VOLTSELECT
                                <br>0x0</td>

                            <td align="center" colspan="1">SDBUSPOWER
                                <br>0x0</td>

                            <td align="center" colspan="1">CARDSRC
                                <br>0x0</td>

                            <td align="center" colspan="1">TESTLEVEL
                                <br>0x0</td>

                            <td align="center" colspan="1">XFERWIDTH
                                <br>0x0</td>

                            <td align="center" colspan="2">DMASELECT
                                <br>0x0</td>

                            <td align="center" colspan="1">HISPEEDEN
                                <br>0x0</td>

                            <td align="center" colspan="1">DATATRANSFERWIDTH
                                <br>0x0</td>

                            <td align="center" colspan="1">LEDCONTROL
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:27</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>26</td>
                            <td>WUENCARDREMOVL</td>
                            <td>RW</td>
                            <td>This bit enables wakeup event via Card Removal assertion in the Normal Interrupt Status register. FN_WUS (Wake up Support) in CIS does not affect this bit.<br><br>
                                 ENABLE               = 0x1 - Enable<br>
                             DISABLE              = 0x0 - Disable</td>
                        </tr>

                        <tr>
                            <td>25</td>
                            <td>WUENCARDINSERT</td>
                            <td>RW</td>
                            <td>This bit enables wakeup event via Card Insertion assertion in the Normal Interrupt Status register. FN_WUS (Wake up Support) in CIS does not affect this bit.<br><br>
                                 ENABLE               = 0x1 - Enable<br>
                             DISABLE              = 0x0 - Disable</td>
                        </tr>

                        <tr>
                            <td>24</td>
                            <td>WUENCARDINT</td>
                            <td>RW</td>
                            <td>This bit enables wakeup event via Card Interrupt assertion in the Normal Interrupt Status register. This bit can be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1.<br><br>
                                 ENABLE               = 0x1 - Enable<br>
                             DISABLE              = 0x0 - Disable</td>
                        </tr>

                        <tr>
                            <td>23</td>
                            <td>BOOTACKCHK</td>
                            <td>RW</td>
                            <td>To check for the boot acknowledge in boot operation.<br><br>
                                 WAIT                 = 0x1 - wait for boot ack from eMMC card<br>
                             NOWAIT               = 0x0 - Will not wait for boot ack from eMMC card</td>
                        </tr>

                        <tr>
                            <td>22</td>
                            <td>ALTBOOTEN</td>
                            <td>RW</td>
                            <td>To start boot code access in alternative mode.<br><br>
                                 START                = 0x1 - To start alternate boot mode access<br>
                             STOP                 = 0x0 - To stop alternate boot mode access</td>
                        </tr>

                        <tr>
                            <td>21</td>
                            <td>BOOTEN</td>
                            <td>RW</td>
                            <td>To start boot code access<br><br>
                                 START                = 0x1 - To start boot code access<br>
                             STOP                 = 0x0 - To stop boot code access</td>
                        </tr>

                        <tr>
                            <td>20</td>
                            <td>SPIMODE</td>
                            <td>RW</td>
                            <td>SPI mode enable bit.<br><br>
                                 SPI                  = 0x1 - SPI mode<br>
                             SD                   = 0x0 - SD mode</td>
                        </tr>

                        <tr>
                            <td>19</td>
                            <td>GAP</td>
                            <td>RW</td>
                            <td>This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the interrupt cycle. Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. If the SD card cannot signal an interrupt during a multiple block transfer, this bit should be set to 0. When the HD detects an SD card insertion, it shall set this bit according to the CCCR of the SDIO card.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>18</td>
                            <td>READWAITCTRL</td>
                            <td>RW</td>
                            <td>The read wait function is optional for SDIO cards. If the card supports read wait, set this bit to enable use of the read wait protocol to stop read data using DAT[2] line. Otherwise the HC has to stop the SD clock to hold read data, which restricts commands generation. When the HD detects an SD card insertion, it shall set this bit according to the CCCR of the SDIO card. If the card does not support read wait, this bit shall never be set to 1 otherwise DAT line conflict may occur. If this bit is set to 0, Suspend / Resume cannot be supported<br><br>
                                 ENABLE               = 0x1 - Enable Read Wait Control<br>
                             DISABLE              = 0x0 - Disable Read Wait Control</td>
                        </tr>

                        <tr>
                            <td>17</td>
                            <td>CONTREQ</td>
                            <td>RWAC</td>
                            <td>This bit is used to restart a transaction which was stopped using the Stop At Block Gap Request. To cancel stop at the block gap, set Stop At block Gap Request to 0 and set this bit to restart the transfer. The HC automatically clears this bit in either of the following cases: 1) In the case of a read transaction, the DAT Line Active changes from 0 to 1 as a read transaction restarts. 2) In the case of a write transaction, the Write transfer active changes from 0 to 1 as the write transaction restarts. Therefore it is not necessary for Host driver to set this bit to 0. If Stop At Block Gap Request is set to 1, any write to this bit is ignored.<br><br>
                                 RESTART              = 0x1 - Restart<br>
                             IGNORED              = 0x0 - Ignored</td>
                        </tr>

                        <tr>
                            <td>16</td>
                            <td>STOPATBLOCKGAPREQUEST</td>
                            <td>RW</td>
                            <td>This bit is used to stop executing a transaction at the next block gap for non- DMA,SDMA and ADMA transfers. Until the transfer complete is set to 1, indicating a transfer completion the HD shall leave this bit set to 1. Clearing both the Stop At Block Gap Request and Continue Request shall not cause the transaction to restart. Read Wait is used to stop the read transaction at the block gap. The HC shall honour Stop At Block Gap Request for write transfers, but for read transfers it requires that the SD card support Read Wait. Therefore the HD shall not set this bit during read transfers unless the SD card supports Read Wait and has set Read Wait Control to 1. In case of write transfers in which the HD writes data to the Buffer Data Port register, the HD shall set this bit after all block data is written. If this bit is set to 1, the HD shall not write data to Buffer data port register. This bit affects Read Transfer Active, Write Transfer Active, DAT line active and Command Inhibit (DAT) in the Present State register.<br><br>
                                 STOP                 = 0x1 - Stop<br>
                             TRANSFER             = 0x0 - Transfer</td>
                        </tr>

                        <tr>
                            <td>15:13</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>12</td>
                            <td>HWRESET</td>
                            <td>RW</td>
                            <td>Hardware reset signal is generated for eMMC card when this bit is set<br><br>
                                 ASSERT               = 0x1 - Drives the hardware reset pin as ZERO (Active LOW to eMMC card)<br>
                             DEASSERT             = 0x0 - Deassert the hardware reset pin</td>
                        </tr>

                        <tr>
                            <td>11:9</td>
                            <td>VOLTSELECT</td>
                            <td>RW</td>
                            <td>By setting these bits, the HD selects the voltage level for the SD card. Before setting this register, the HD shall check the voltage support bits in the capabilities register. If an unsupported voltage is selected, the Host System shall not supply SD bus voltage. All voltage select values not enumerated here are reserved.<br><br>
                                 3_3V                 = 0x7 - 3.3 V(Typ.)<br>
                             3_0V                 = 0x6 - 3.0 V(Typ.)<br>
                             1_8V                 = 0x5 - 1.8 V(Typ.)</td>
                        </tr>

                        <tr>
                            <td>8</td>
                            <td>SDBUSPOWER</td>
                            <td>RW</td>
                            <td>Before setting this bit, the SD host driver shall set SD Bus Voltage Select. If the HC detects the No Card State, this bit shall be cleared.<br><br>
                                 POWERON              = 0x1 - Power on<br>
                             POWEROFF             = 0x0 - Power off</td>
                        </tr>

                        <tr>
                            <td>7</td>
                            <td>CARDSRC</td>
                            <td>RW</td>
                            <td>This bit selects source for card detection.<br><br>
                                 TEST                 = 0x1 - The card detect test level is selected<br>
                             SDCD                 = 0x0 - SDCD is selected (for normal use)</td>
                        </tr>

                        <tr>
                            <td>6</td>
                            <td>TESTLEVEL</td>
                            <td>RW</td>
                            <td>This bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates card inserted or not. Generates (card ins or card removal) interrupt when the normal int sts enable bit is set.<br><br>
                                 CARDINSERTED         = 0x1 - Card Inserted<br>
                             NOCARD               = 0x0 - No Card</td>
                        </tr>

                        <tr>
                            <td>5</td>
                            <td>XFERWIDTH</td>
                            <td>RW</td>
                            <td>This bit controls 8-bit bus width mode for embedded device. Support of this function is indicated in 8-bit Support for Embedded Device in the Capabilities register. If a device supports 8-bit bus mode, this bit may be set to 1. If this bit is 0, bus width is controlled by Data Transfer Width in the Host Control 1 register.This bit is not effective when multiple devices are installed on a bus slot (Slot Type is set to 10b in the Capabilities register). In this case, each device bus width is controlled by Bus Width Preset field in the Shared Bus register.<br><br>
                                 8BIT                 = 0x1 - 8-bit Bus Width<br>
                             XFER                 = 0x0 - Bus Width is selected by Data Transfer Width</td>
                        </tr>

                        <tr>
                            <td>4:3</td>
                            <td>DMASELECT</td>
                            <td>RW</td>
                            <td>One of supported DMA modes can be selected. The host driver shall check support of DMA modes by referring the Capabilities register.<br><br>
                                 SDMA                 = 0x0 - SDMA is selected<br>
                             ADMA132              = 0x1 - 32-bit Address ADMA1 is selected<br>
                             ADMA232              = 0x2 - 32-bit Address ADMA2 is selected<br>
                             ADMA264              = 0x3 - 64-bit Address ADMA2 is selected</td>
                        </tr>

                        <tr>
                            <td>2</td>
                            <td>HISPEEDEN</td>
                            <td>RW</td>
                            <td>This bit is optional. Before setting this bit, the HD shall check the High Speed Support in the capabilities register. If this bit is set to 0 (default), the HC outputs CMD line and DAT lines at the falling edge of the SD clock (up to 25 MHz/ 20MHz for MMC). If this bit is set to 1, the HC outputs CMD line and DAT lines at the rising edge of the SD clock (up to 50 MHz for SD/52MHz for MMC)/ 208Mhz (for SD3.0) If Preset Value Enable in the Host Control 2 register is set to 1, Host Driver needs to reset SD Clock Enable before changing this field to avoid generating clock glitches. After setting this field, the Host Driver sets SD Clock Enable again<br><br>
                                 HIGH                 = 0x1 - High Speed Mode<br>
                             NORMAL               = 0x0 - Normal Speed Mode</td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>DATATRANSFERWIDTH</td>
                            <td>RW</td>
                            <td>(SD1 or SD4) This bit selects the data width of the HC. The HD shall select it to match the data width of the SD card.<br><br>
                                 SD4                  = 0x1 - 4 bit mode<br>
                             SD1                  = 0x0 - 1 bit mode</td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>LEDCONTROL</td>
                            <td>RW</td>
                            <td>This bit is used to caution the user not to remove the card while the SD card is being accessed. If the software is going to issue multiple SD commands, this bit can be set during all transactions. It is not necessary to change for each transaction.<br><br>
                                 ON                   = 0x1 - LED on<br>
                             OFF                  = 0x0 - LED off</td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="CLOCKCTRL" class="panel-title">CLOCKCTRL - Clock control</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x4007002C</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Clock control</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="5">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">SWRSTDAT
                                <br>0x0</td>

                            <td align="center" colspan="1">SWRSTCMD
                                <br>0x0</td>

                            <td align="center" colspan="1">SWRSTALL
                                <br>0x0</td>

                            <td align="center" colspan="4">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="4">TIMEOUTCNT
                                <br>0x0</td>

                            <td align="center" colspan="8">FREQSEL
                                <br>0x0</td>

                            <td align="center" colspan="2">UPRCLKDIV
                                <br>0x0</td>

                            <td align="center" colspan="1">CLKGENSEL
                                <br>0x0</td>

                            <td align="center" colspan="2">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">SDCLKEN
                                <br>0x0</td>

                            <td align="center" colspan="1">CLKSTABLE
                                <br>0x0</td>

                            <td align="center" colspan="1">CLKEN
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:27</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>26</td>
                            <td>SWRSTDAT</td>
                            <td>RWAC</td>
                            <td>Only part of data circuit is reset. The following registers and bits are cleared by this bit: Buffer Data Port Register Buffer is cleared and Initialized. Present State register Buffer read Enable Buffer write Enable Read Transfer Active Write Transfer Active DAT Line Active Command Inhibit (DAT) Block Gap Control register Continue Request Stop At Block Gap Request Normal Interrupt Status register Buffer Read Ready Buffer Write Ready Block Gap Event Transfer Complete<br><br>
                                 RESET                = 0x1 - Reset<br>
                             WORK                 = 0x0 - Work</td>
                        </tr>

                        <tr>
                            <td>25</td>
                            <td>SWRSTCMD</td>
                            <td>RWAC</td>
                            <td>Only part of command circuit is reset. The following registers and bits are cleared by this bit: Present State register Command Inhibit (CMD) Normal Interrupt Status register Command Complete<br><br>
                                 RESET                = 0x1 - Reset<br>
                             WORK                 = 0x0 - Work</td>
                        </tr>

                        <tr>
                            <td>24</td>
                            <td>SWRSTALL</td>
                            <td>RWAC</td>
                            <td>This reset affects the entire HC except for the card detection circuit. Register bits of type ROC, RW, RW1C, RWAC are cleared to 0. During its initialization, the HD shall set this bit to 1 to reset the HC. The HC shall reset this bit to 0 when capabilities registers are valid and the HD can read them. Additional use of Software Reset For All may not affect the value of the Capabilities registers. If this bit is set to 1, the SD card shall reset itself and must be re initialized by the HD. A reset pulse is generated when writing 1 to each bit of this register. After completing the reset, the HC shall clear each bit. Because it takes some time to complete software reset, the SD Host Driver shall confirm that these bits are 0.<br><br>
                                 RESET                = 0x1 - Reset<br>
                             WORK                 = 0x0 - Work</td>
                        </tr>

                        <tr>
                            <td>23:20</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>19:16</td>
                            <td>TIMEOUTCNT</td>
                            <td>RW</td>
                            <td>This value determines the interval by which DAT line time-outs are detected. Refer to the Data Time-out Error in the Error Interrupt Status register for information on factors that dictate time-out generation. Time-out clock frequency will be generated by dividing the sdclockTMCLK by this value. When setting this register, prevent inadvertent time-out events by clearing the Data Time-out Error Status Enable (in the Error Interrupt Status Enable register) At the initialization of the HC, the HD shall set the Data Time-out Counter Value according to the Capabilities register. The general formula is TIMEOUT = 2 ^ (TIMEOUTCNT + 13).<br><br>
                                 27                   = 0xE - TMCLK * 2^27<br>
                             26                   = 0x0 - TMCLK * 2^26<br>
                             25                   = 0x0 - TMCLK * 2^25<br>
                             24                   = 0x0 - TMCLK * 2^24<br>
                             23                   = 0x0 - TMCLK * 2^23<br>
                             22                   = 0x0 - TMCLK * 2^22<br>
                             21                   = 0x0 - TMCLK * 2^21<br>
                             20                   = 0x0 - TMCLK * 2^20<br>
                             19                   = 0x0 - TMCLK * 2^19<br>
                             18                   = 0x0 - TMCLK * 2^18<br>
                             17                   = 0x0 - TMCLK * 2^17<br>
                             16                   = 0x0 - TMCLK * 2^16<br>
                             15                   = 0x0 - TMCLK * 2^15<br>
                             14                   = 0x0 - TMCLK * 2^14<br>
                             13                   = 0x0 - TMCLK * 2^13</td>
                        </tr>

                        <tr>
                            <td>15:8</td>
                            <td>FREQSEL</td>
                            <td>RW</td>
                            <td>This register is used to select the frequency of the SDCLK pin. The frequency is not programmed directly; rather this register holds the divisor of the Base Clock Frequency For SD clock in the capabilities register. Only the following settings are allowed. (1) 8-bit Divided Clock Mode Setting 00h specifies the highest frequency of the SD Clock. When setting multiple bits, the most significant bit is used as the divisor. But multiple bits should not be set. The two default divider values can be calculated by the frequency that is defined by the Base Clock Frequency For SD Clock in the Capabilities register. 1) 25 MHz divider value 2) 400 KHz divider value The frequency of the SDCLK is set by the following formula: Clock Frequency = (Baseclock) / divisor. Thus choose the smallest possible divisor which results in a clock frequency that is less than or equal to the target frequency. Maximum Frequency for SD = 50Mhz (base clock) Maximum Frequency for MMC = 52Mhz (base clock) Minimum Frequency = 195.3125Khz (50Mhz / 256), same calculation for MMC also (2) 10-bit Divided Clock Mode Host Controller Version 3.00 supports this mandatory mode instead of the 8-bit Divided Clock Mode. The length of divider is extended to10 bits and all divider values shall be supported. 3FFh --1/2046 Divided Clock N -------1/2N Divided Clock (Duty 50%) 002h -- 1/4 Divided Clock 001h ---1/2 Divided Clock 000h --- Base Clock (10MHz-254MHz)<br><br>
                                 DIV256               = 0x80 - base clock divided by 256<br>
                             DIV128               = 0x40 - base clock divided by 128<br>
                             DIV64                = 0x20 - base clock divided by 64<br>
                             DIV32                = 0x10 - base clock divided by 32<br>
                             DIV16                = 0x8 - base clock divided by 16<br>
                             DIV8                 = 0x4 - base clock divided by 8<br>
                             DIV4                 = 0x2 - base clock divided by 4<br>
                             DIV2                 = 0x1 - base clock divided by 2<br>
                             BASECLK              = 0x0 - Base clock (10MHz - 63MHz)</td>
                        </tr>

                        <tr>
                            <td>7:6</td>
                            <td>UPRCLKDIV</td>
                            <td>RW</td>
                            <td>Bit 07-06 is assigned to bit 09-08 of clock divider in SDCLK Frequency Select<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>5</td>
                            <td>CLKGENSEL</td>
                            <td>RW</td>
                            <td>This bit is used to select the clock generator mode in SDCLK Frequency Select. If the Programmable Clock Mode is supported (non-zero value is set to Clock Multiplier in the Capabilities register), this bit attribute is RW, and if not supported, this bit attribute is RO and zero is read. This bit depends on the setting of Preset Value Enable in the Host Control 2 register. If the Preset Value Enable = 0, this bit is set by Host Driver. If the Preset Value Enable = 1, this bit is automatically set to a value specified in one of Preset Value registers.<br><br>
                                 PROGCLK              = 0x1 - Programmable Clock Mode<br>
                             DIVCLK               = 0x0 - Divided Clock Mode</td>
                        </tr>

                        <tr>
                            <td>4:3</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>2</td>
                            <td>SDCLKEN</td>
                            <td>RW</td>
                            <td>The HC shall stop SDCLK when writing this bit to 0. SDCLK frequency Select can be changed when this bit is 0. Then, the HC shall maintain the same clock frequency until SDCLK is stopped (Stop at SDCLK = 0). If the HC detects the No Card state, this bit shall be cleared.<br><br>
                                 ENABLE               = 0x1 - Enable<br>
                             DISABLE              = 0x0 - Disable</td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>CLKSTABLE</td>
                            <td>ROC</td>
                            <td>This bit is set to 1 when SD clock is stable after writing to Internal Clock Enable in this register to 1. The SD Host Driver shall wait to set SD Clock Enable until this bit is set to 1. Note: This is useful when using PLL for a clock oscillator that requires setup time.<br><br>
                                 READY                = 0x1 - Ready<br>
                             NOTREADY             = 0x0 - Not Ready</td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>CLKEN</td>
                            <td>RW</td>
                            <td>This bit is set to 0 when the HD is not using the HC or the HC awaits a wakeup event. The HC should stop its internal clock to go very low power state. Still, registers shall be able to be read and written. Clock starts to oscillate when this bit is set to 1. When clock oscillation is stable, the HC shall set Internal Clock Stable in this register to 1. This bit shall not affect card detection.<br><br>
                                 OSC                  = 0x1 - Oscillate<br>
                             STOP                 = 0x0 - Stop</td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="INTSTAT" class="panel-title">INTSTAT - Interrupt enable</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40070030</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Interrupt enable</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="3">VNDERRSTAT
                                <br>0x0</td>

                            <td align="center" colspan="1">TGTRESPERR
                                <br>0x0</td>

                            <td align="center" colspan="2">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">ADMAERROR
                                <br>0x0</td>

                            <td align="center" colspan="1">AUTOCMDERROR
                                <br>0x0</td>

                            <td align="center" colspan="1">CURRENTLIMITERROR
                                <br>0x0</td>

                            <td align="center" colspan="1">DATAENDBITERROR
                                <br>0x0</td>

                            <td align="center" colspan="1">DATACRCERROR
                                <br>0x0</td>

                            <td align="center" colspan="1">DATATIMEOUTERROR
                                <br>0x0</td>

                            <td align="center" colspan="1">COMMANDINDEXERROR
                                <br>0x0</td>

                            <td align="center" colspan="1">COMMANDENDBITERROR
                                <br>0x0</td>

                            <td align="center" colspan="1">COMMANDCRCERROR
                                <br>0x0</td>

                            <td align="center" colspan="1">COMMANDTIMEOUTERROR
                                <br>0x0</td>

                            <td align="center" colspan="1">ERRORINTERRUPT
                                <br>0x0</td>

                            <td align="center" colspan="1">BOOTTERMINATE
                                <br>0x0</td>

                            <td align="center" colspan="1">BOOTACKRCV
                                <br>0x0</td>

                            <td align="center" colspan="1">RETUNINGEVENT
                                <br>0x0</td>

                            <td align="center" colspan="1">INTC
                                <br>0x0</td>

                            <td align="center" colspan="1">INTB
                                <br>0x0</td>

                            <td align="center" colspan="1">INTA
                                <br>0x0</td>

                            <td align="center" colspan="1">CARDINTERRUPT
                                <br>0x0</td>

                            <td align="center" colspan="1">CARDREMOVAL
                                <br>0x0</td>

                            <td align="center" colspan="1">CARDINSERTION
                                <br>0x0</td>

                            <td align="center" colspan="1">BUFFERREADREADY
                                <br>0x0</td>

                            <td align="center" colspan="1">BUFFERWRITEREADY
                                <br>0x0</td>

                            <td align="center" colspan="1">DMAINTERRUPT
                                <br>0x0</td>

                            <td align="center" colspan="1">BLOCKGAPEVENT
                                <br>0x0</td>

                            <td align="center" colspan="1">TRANSFERCOMPLETE
                                <br>0x0</td>

                            <td align="center" colspan="1">COMMANDCOMPLETE
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:29</td>
                            <td>VNDERRSTAT</td>
                            <td>RO</td>
                            <td>Vendor specific error status.<br><br>
                                 READY                = 0x1 - Ready<br>
                             NOTREADY             = 0x0 - Not Ready</td>
                        </tr>

                        <tr>
                            <td>28</td>
                            <td>TGTRESPERR</td>
                            <td>RW1C</td>
                            <td>Occurs when detecting error in aximst_bresp or aximst_rresp<br><br>
                                 NOERROR              = 0x0 - no error<br>
                             ERROR                = 0x1 - error</td>
                        </tr>

                        <tr>
                            <td>27:26</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>25</td>
                            <td>ADMAERROR</td>
                            <td>RW1C</td>
                            <td>This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the ADMA Error Status Register.<br><br>
                                 ERROR                = 0x1 - Error<br>
                             NOERROR              = 0x0 - No error</td>
                        </tr>

                        <tr>
                            <td>24</td>
                            <td>AUTOCMDERROR</td>
                            <td>RW1C</td>
                            <td>Auto CMD12 and Auto CMD23 use this error status. This bit is set when detecting that one of the bits D00-D04 in Auto CMD Error Status register has changed from 0 to 1. In case of Auto CMD12, this bit is set to 1, not only when the errors in Auto CMD12 occur but also when Auto CMD12 is not executed due to the previous command error.<br><br>
                                 NOERROR              = 0x0 - No Error<br>
                             ERROR                = 0x1 - Error</td>
                        </tr>

                        <tr>
                            <td>23</td>
                            <td>CURRENTLIMITERROR</td>
                            <td>RW</td>
                            <td>By setting the SD Bus Power bit in the Power Control Register, the HC is requested to supply power for the SD Bus. If the HC supports the Current Limit Function, it can be protected from an Illegal card by stopping power supply to the card in which case this bit indicates a failure status. Reading 1 means the HC is not supplying power to SD card due to some failure. Reading 0 means that the HC is supplying power and no error has occurred. This bit shall always set to be 0, if the HC does not support this function.<br><br>
                                 NOERROR              = 0x0 - No Error<br>
                             ERROR                = 0x1 - Power Fail</td>
                        </tr>

                        <tr>
                            <td>22</td>
                            <td>DATAENDBITERROR</td>
                            <td>RW1C</td>
                            <td>Occurs when detecting 0 at the end bit position of read data which uses the DAT line or the end bit position of the CRC status.<br><br>
                                 NOERROR              = 0x0 - No Error<br>
                             ERROR                = 0x1 - Error</td>
                        </tr>

                        <tr>
                            <td>21</td>
                            <td>DATACRCERROR</td>
                            <td>RW1C</td>
                            <td>Occurs when detecting CRC error when transferring read data which uses the DAT line or when detecting the Write CRC Status having a value of other than 0.<br><br>
                                 NOERROR              = 0x0 - No Error<br>
                             ERROR                = 0x1 - Error</td>
                        </tr>

                        <tr>
                            <td>20</td>
                            <td>DATATIMEOUTERROR</td>
                            <td>RW1C</td>
                            <td>Occurs when detecting one of following timeout conditions. 1. Busy Timeout for R1b, R5b type. 2. Busy Timeout after Write CRC status 3. Write CRC status Timeout 4. Read Data Timeout<br><br>
                                 NOERROR              = 0x0 - No Error<br>
                             ERROR                = 0x1 - Timeout</td>
                        </tr>

                        <tr>
                            <td>19</td>
                            <td>COMMANDINDEXERROR</td>
                            <td>RW</td>
                            <td>Occurs if a Command Index error occurs in the Command Response.<br><br>
                                 NOERROR              = 0x0 - No Error<br>
                             ERROR                = 0x1 - Error</td>
                        </tr>

                        <tr>
                            <td>18</td>
                            <td>COMMANDENDBITERROR</td>
                            <td>RW</td>
                            <td>Occurs only if the no response is returned within 64 SDCLK cycles from the end bit of the command. If the HC detects a CMD line conflict, in which case Command CRC Error shall also be set. This bit shall be set without waiting for 64 SDCLK cycles because the command will be aborted by the HC.<br><br>
                                 NOERROR              = 0x0 - No Error<br>
                             ERROR                = 0x1 - Timeout</td>
                        </tr>

                        <tr>
                            <td>17</td>
                            <td>COMMANDCRCERROR</td>
                            <td>RW</td>
                            <td>Occurs when detecting that the end bit of a command response is 0.<br><br>
                                 NOERROR              = 0x0 - No Error<br>
                             ERROR                = 0x1 - End Bit Error Generated</td>
                        </tr>

                        <tr>
                            <td>16</td>
                            <td>COMMANDTIMEOUTERROR</td>
                            <td>RW</td>
                            <td>Command CRC Error is generated in two cases. 1. If a response is returned and the Command Time-out Error is set to 0, this bit is set to 1 when detecting a CRT error in the command response 2. The HC detects a CMD line conflict by monitoring the CMD line when a command is issued. If the HC drives the CMD line to 1 level, but detects 0 level on the CMD line at the next SDCLK edge, then the HC shall abort the command (Stop driving CMD line) and set this bit to 1. The Command Timeout Error shall also be set to 1 to distinguish CMD line conflict.<br><br>
                                 NOERROR              = 0x0 - No Error<br>
                             ERROR                = 0x1 - CRC Error Generated</td>
                        </tr>

                        <tr>
                            <td>15</td>
                            <td>ERRORINTERRUPT</td>
                            <td>ROC</td>
                            <td>If any of the bits in the Error Interrupt Status Register are set, then this bit is set. Therefore the HD can test for an error by checking this bit first.<br><br>
                                 NOERROR              = 0x0 - No Error.<br>
                             ERROR                = 0x1 - Error.</td>
                        </tr>

                        <tr>
                            <td>14</td>
                            <td>BOOTTERMINATE</td>
                            <td>RW1C</td>
                            <td>Interrupt This status is set if the boot operation get terminated<br><br>
                                 OK                   = 0x0 - Boot operation is not terminated.<br>
                             BOOTTERM             = 0x1 - Boot operation is terminated</td>
                        </tr>

                        <tr>
                            <td>13</td>
                            <td>BOOTACKRCV</td>
                            <td>RW1C</td>
                            <td>This status is set if the boot acknowledge is received from device.<br><br>
                                 NOACK                = 0x0 - Boot ack is not received.<br>
                             ACK                  = 0x1 - Boot ack is received.</td>
                        </tr>

                        <tr>
                            <td>12</td>
                            <td>RETUNINGEVENT</td>
                            <td>ROC</td>
                            <td>This status is set if Re-Tuning Request in the Present State register changes from 0 to 1. Host Controller requests Host Driver to perform re-tuning for next data transfer. Current data transfer (not large block count) can be completed without re-tuning.<br><br>
                                 RETUNE               = 0x1 - ReTuning should be performed<br>
                             NORETUNE             = 0x0 - ReTuning is not required</td>
                        </tr>

                        <tr>
                            <td>11</td>
                            <td>INTC</td>
                            <td>ROC</td>
                            <td>This status is set if INT_C is enabled and INT_C# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_C interrupt factor<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>10</td>
                            <td>INTB</td>
                            <td>ROC</td>
                            <td>This status is set if INT_B is enabled and INT_B# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_B interrupt factor<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>9</td>
                            <td>INTA</td>
                            <td>ROC</td>
                            <td>This status is set if INT_A is enabled and INT_A# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_A interrupt factor<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>8</td>
                            <td>CARDINTERRUPT</td>
                            <td>ROC</td>
                            <td>Writing this bit to 1 does not clear this bit. It is cleared by resetting the SD card interrupt factor. In 1-bit mode, the HC shall detect the Card Interrupt without SD Clock to support wakeup. In 4-bit mode, the card interrupt signal is sampled during the interrupt cycle, so there are some sample delays between the interrupt signal from the card and the interrupt to the Host system. when this status has been set and the HD needs to start this interrupt service, Card Interrupt Status Enable in the Normal Interrupt Status register shall be set to 0 in order to clear the card interrupt statuses latched in the HC and stop driving the Host System. After completion of the card interrupt service (the reset factor in the SD card and the interrupt signal may not be asserted), set Card Interrupt Status Enable to 1 and start sampling the interrupt signal again. Interrupt detected by DAT[1] is supported when there is a card per slot. In case of shared bus, interrupt pins are used to detect interrupts. If 000b is set to Interrupt Pin Select in the Shared Bus Control register, this status is effective. Non-zero value is set to Interrupt Pin Select, INT_A, INT_B or INT_C is then used to device interrupts.<br><br>
                                 NOINT                = 0x0 - No Card Interrupt<br>
                             INT                  = 0x1 - Generate Card Interrupt</td>
                        </tr>

                        <tr>
                            <td>7</td>
                            <td>CARDREMOVAL</td>
                            <td>RW1C</td>
                            <td>This status is set if the Card Inserted in the Present State register changes from 1 to 0. When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed. Because the card detect may possibly be changed when the HD clear this bit an Interrupt event may not be generated.<br><br>
                                 STABLE               = 0x0 - Card State Stable or Debouncing<br>
                             REMOVED              = 0x1 - Card Removed</td>
                        </tr>

                        <tr>
                            <td>6</td>
                            <td>CARDINSERTION</td>
                            <td>RW1C</td>
                            <td>This status is set if the Card Inserted in the Present State register changes from 0 to 1. When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed. Because the card detect may possibly be changed when the HD clear this bit an Interrupt event may not be generated.<br><br>
                                 STABLE               = 0x0 - Card State Stable or Debouncing<br>
                             INSERTED             = 0x1 - Card Inserted</td>
                        </tr>

                        <tr>
                            <td>5</td>
                            <td>BUFFERREADREADY</td>
                            <td>RW1C</td>
                            <td>This status is set if the Buffer Read Enable changes from 0 to 1. Buffer Read Ready is set to 1 for every CMD19 execution in tuning procedure.<br><br>
                                 NOREADY              = 0x0 - Not Ready to read Buffer.<br>
                             READY                = 0x1 - Ready to read Buffer.</td>
                        </tr>

                        <tr>
                            <td>4</td>
                            <td>BUFFERWRITEREADY</td>
                            <td>RW1C</td>
                            <td>This status is set if the Buffer Write Enable changes from 0 to 1.<br><br>
                                 NOTREADY             = 0x0 - Not Ready to Write Buffer.<br>
                             READY                = 0x1 - Ready to Write Buffer.</td>
                        </tr>

                        <tr>
                            <td>3</td>
                            <td>DMAINTERRUPT</td>
                            <td>RW1C</td>
                            <td>This status is set if the HC detects the Host DMA Buffer Boundary in the Block Size regiser.<br><br>
                                 NOINT                = 0x0 - No DMA Interrupt<br>
                             INT                  = 0x1 - DMA Interrupt is Generated</td>
                        </tr>

                        <tr>
                            <td>2</td>
                            <td>BLOCKGAPEVENT</td>
                            <td>RW1C</td>
                            <td>If the Stop At Block Gap Request in the Block Gap Control Register is set, this bit is set. Read Transaction: This bit is set at the falling edge of the DAT Line Active Status (When the transaction is stopped at SD Bus timing. The Read Wait must be supported inorder to use this function). Write Transaction: This bit is set at the falling edge of Write Transfer Active Status (After getting CRC status at SD Bus timing).<br><br>
                                 NOEVENT              = 0x0 - No Block Gap Event<br>
                             STOPPED              = 0x1 - Transaction stopped at Block Gap</td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>TRANSFERCOMPLETE</td>
                            <td>RW1C</td>
                            <td>This bit is set when a read / write transaction is completed. Read Transaction: This bit is set at the falling edge of Read Transfer Active Status. There are two cases in which the Interrupt is generated. The first is when a data transfer is completed as specified by data length (After the last data has been read to the Host System). The second is when data has stopped at the block gap and completed the data transfer by setting the Stop At Block Gap Request in the Block Gap Control Register (After valid data has been read to the Host System). Write Transaction: This bit is set at the falling edge of the DAT Line Active Status. There are two cases in which the Interrupt is generated. The first is when the last data is written to the card as specified by data length and Busy signal is released. The second is when data transfers are stopped at the block gap by setting Stop At Block Gap Request in the Block Gap Control Register and data transfers completed. (After valid data is written to the SD card and the busy signal is released). Note: Transfer Complete has higher priority than Data Time-out Error. If both bits are set to 1, the data transfer can be considered complete Note: While performing tuning procedure (Execute Tuning is set to 1), Transfer Complete is not set to 1<br><br>
                                 NODATA               = 0x0 - No Data Transfer Complete<br>
                             COMPLETE             = 0x1 - Data Transfer Complete</td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>COMMANDCOMPLETE</td>
                            <td>RW1C</td>
                            <td>This bit is set when we get the end bit of the command response (Except Auto CMD12 and Auto CMD23) Note: Command Time-out Error has higher priority than Command Complete. If both are set to 1, it can be considered that the response was not received correctly.<br><br>
                                 NOCMP                = 0x0 - No Command Complete<br>
                             CMDCMP               = 0x1 - Command Complete</td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="INTENABLE" class="panel-title">INTENABLE - Normal interrupt status enable</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40070034</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Normal interrupt status enable</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="3">VENDORSPECIFICERRORSTATUSENABLE
                                <br>0x0</td>

                            <td align="center" colspan="1">TGTRESPERRHOSTERRSTATEN
                                <br>0x0</td>

                            <td align="center" colspan="1">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">TUNINGERRORSTATUS
                                <br>0x0</td>

                            <td align="center" colspan="1">ADMAERRORSTATUSENABLE
                                <br>0x0</td>

                            <td align="center" colspan="1">AUTOCMD12ERRORSTATUSENABLE
                                <br>0x0</td>

                            <td align="center" colspan="1">CURRENTLIMITERRORSTATUSENABLE
                                <br>0x0</td>

                            <td align="center" colspan="1">DATAENDBITERRORSTATUSENABLE
                                <br>0x0</td>

                            <td align="center" colspan="1">DATACRCERRORSTATUSENABLE
                                <br>0x0</td>

                            <td align="center" colspan="1">DATATIMEOUTERRORSTATUSENABLE
                                <br>0x0</td>

                            <td align="center" colspan="1">COMMANDINDEXERRORSTATUSENABLE
                                <br>0x0</td>

                            <td align="center" colspan="1">COMMANDENDBITERRORSTATUSENABLE
                                <br>0x0</td>

                            <td align="center" colspan="1">COMMANDCRCERRORSTATUSENABLE
                                <br>0x0</td>

                            <td align="center" colspan="1">COMMANDTIMEOUTERRORSTATUSENABLE
                                <br>0x0</td>

                            <td align="center" colspan="1">FIXEDTO0
                                <br>0x0</td>

                            <td align="center" colspan="1">BOOTTERMINATE
                                <br>0x0</td>

                            <td align="center" colspan="1">BOOTACKRCVENABLE
                                <br>0x0</td>

                            <td align="center" colspan="1">RETUNINGEVENTSTATUSENABLE
                                <br>0x0</td>

                            <td align="center" colspan="1">INTCSTATUSENABLE
                                <br>0x0</td>

                            <td align="center" colspan="1">INTBSTATUSENABLE
                                <br>0x0</td>

                            <td align="center" colspan="1">INTASTATUSENABLE
                                <br>0x0</td>

                            <td align="center" colspan="1">CARDINTERRUPTSTATUSENABLE
                                <br>0x0</td>

                            <td align="center" colspan="1">CARDREMOVALSTATUSENABLE
                                <br>0x0</td>

                            <td align="center" colspan="1">CARDINSERTIONSTATUSENABLE
                                <br>0x0</td>

                            <td align="center" colspan="1">BUFFERREADREADYSTATUSENABLE
                                <br>0x0</td>

                            <td align="center" colspan="1">BUFFERWRITEREADYSTATUSENABLE
                                <br>0x0</td>

                            <td align="center" colspan="1">DMAINTERRUPTSTATUSENABLE
                                <br>0x0</td>

                            <td align="center" colspan="1">BLOCKGAPEVENTSTATUSENABLE
                                <br>0x0</td>

                            <td align="center" colspan="1">TRANSFERCOMPLETESTATUSENABLE
                                <br>0x0</td>

                            <td align="center" colspan="1">COMMANDCOMPLETESTATUSENABLE
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:29</td>
                            <td>VENDORSPECIFICERRORSTATUSENABLE</td>
                            <td>RW</td>
                            <td>Vendor-specific error status enable.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>28</td>
                            <td>TGTRESPERRHOSTERRSTATEN</td>
                            <td>RW</td>
                            <td>Desc<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>27</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>26</td>
                            <td>TUNINGERRORSTATUS</td>
                            <td>RW</td>
                            <td>enable<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>25</td>
                            <td>ADMAERRORSTATUSENABLE</td>
                            <td>RW</td>
                            <td>Desc<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>24</td>
                            <td>AUTOCMD12ERRORSTATUSENABLE</td>
                            <td>RW</td>
                            <td>Desc<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>23</td>
                            <td>CURRENTLIMITERRORSTATUSENABLE</td>
                            <td>RW</td>
                            <td>Desc<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>22</td>
                            <td>DATAENDBITERRORSTATUSENABLE</td>
                            <td>RW</td>
                            <td>Desc<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>21</td>
                            <td>DATACRCERRORSTATUSENABLE</td>
                            <td>RW</td>
                            <td>Desc<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>20</td>
                            <td>DATATIMEOUTERRORSTATUSENABLE</td>
                            <td>RW</td>
                            <td>Desc<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>19</td>
                            <td>COMMANDINDEXERRORSTATUSENABLE</td>
                            <td>RW</td>
                            <td>Desc<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>18</td>
                            <td>COMMANDENDBITERRORSTATUSENABLE</td>
                            <td>RW</td>
                            <td>Desc<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>17</td>
                            <td>COMMANDCRCERRORSTATUSENABLE</td>
                            <td>RW</td>
                            <td>Desc<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>16</td>
                            <td>COMMANDTIMEOUTERRORSTATUSENABLE</td>
                            <td>RW</td>
                            <td>Desc<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>15</td>
                            <td>FIXEDTO0</td>
                            <td>RO</td>
                            <td>The HC shall control error Interrupts using the Error Interrupt Status Enable register.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>14</td>
                            <td>BOOTTERMINATE</td>
                            <td>RW</td>
                            <td>Boot is terminated?<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>13</td>
                            <td>BOOTACKRCVENABLE</td>
                            <td>RW</td>
                            <td>Interrupt<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>12</td>
                            <td>RETUNINGEVENTSTATUSENABLE</td>
                            <td>RW</td>
                            <td>Interrupt<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>11</td>
                            <td>INTCSTATUSENABLE</td>
                            <td>RW</td>
                            <td>If this bit is set to 0, the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_C and may set this bit again after all interrupt requests to INT_C pin are cleared to prevent inadvertent interrupts. Interrupt enable<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>10</td>
                            <td>INTBSTATUSENABLE</td>
                            <td>RW</td>
                            <td>If this bit is set to 0, the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_B and may set this bit again after all interrupt requests to INT_B pin are cleared to prevent inadvertent interrupts.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>9</td>
                            <td>INTASTATUSENABLE</td>
                            <td>RW</td>
                            <td>If this bit is set to 0, the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_A and may set this bit again after all interrupt requests to INT_A pin are cleared to prevent inadvertent interrupts.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>8</td>
                            <td>CARDINTERRUPTSTATUSENABLE</td>
                            <td>RW</td>
                            <td>If this bit is set to 0, the HC shall clear Interrupt request to the System. The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. The HD may clear the Card Interrupt Status Enable before servicing the Card Interrupt and may set this bit again after all Interrupt requests from the card are cleared to prevent inadvertent Interrupts.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>7</td>
                            <td>CARDREMOVALSTATUSENABLE</td>
                            <td>RW</td>
                            <td>Description<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>6</td>
                            <td>CARDINSERTIONSTATUSENABLE</td>
                            <td>RW</td>
                            <td>Description<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>5</td>
                            <td>BUFFERREADREADYSTATUSENABLE</td>
                            <td>RW</td>
                            <td>Description<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>4</td>
                            <td>BUFFERWRITEREADYSTATUSENABLE</td>
                            <td>RW</td>
                            <td>Description<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>3</td>
                            <td>DMAINTERRUPTSTATUSENABLE</td>
                            <td>RW</td>
                            <td>Description<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>2</td>
                            <td>BLOCKGAPEVENTSTATUSENABLE</td>
                            <td>RW</td>
                            <td>Description<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>TRANSFERCOMPLETESTATUSENABLE</td>
                            <td>RW</td>
                            <td>Description<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>COMMANDCOMPLETESTATUSENABLE</td>
                            <td>RW</td>
                            <td>Description<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="INTSIG" class="panel-title">INTSIG - Normal interrupt signal enable</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40070038</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Normal interrupt signal enable</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="3">VNDERREN
                                <br>0x0</td>

                            <td align="center" colspan="1">TGTRESPEN
                                <br>0x0</td>

                            <td align="center" colspan="1">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">TUNINGERREN
                                <br>0x0</td>

                            <td align="center" colspan="1">ADMAERREN
                                <br>0x0</td>

                            <td align="center" colspan="1">AUTOCMD12ERREN
                                <br>0x0</td>

                            <td align="center" colspan="1">CURRLMTERREN
                                <br>0x0</td>

                            <td align="center" colspan="1">DATAENDERREN
                                <br>0x0</td>

                            <td align="center" colspan="1">DATACRCERREN
                                <br>0x0</td>

                            <td align="center" colspan="1">DATATOERROREN
                                <br>0x0</td>

                            <td align="center" colspan="1">CMDIDXERREN
                                <br>0x0</td>

                            <td align="center" colspan="1">CMDENDBITERREN
                                <br>0x0</td>

                            <td align="center" colspan="1">CMDCRCERREN
                                <br>0x0</td>

                            <td align="center" colspan="1">CMDTOERREN
                                <br>0x0</td>

                            <td align="center" colspan="1">FIXED0
                                <br>0x0</td>

                            <td align="center" colspan="1">BOOTTERM
                                <br>0x0</td>

                            <td align="center" colspan="1">BOOTACKEN
                                <br>0x0</td>

                            <td align="center" colspan="1">RETUNEEVENTEN
                                <br>0x0</td>

                            <td align="center" colspan="1">INTCEN
                                <br>0x0</td>

                            <td align="center" colspan="1">INTBEN
                                <br>0x0</td>

                            <td align="center" colspan="1">INTAEN
                                <br>0x0</td>

                            <td align="center" colspan="1">CARDINTEN
                                <br>0x0</td>

                            <td align="center" colspan="1">CARDREMOVALEN
                                <br>0x0</td>

                            <td align="center" colspan="1">CARDINSERTEN
                                <br>0x0</td>

                            <td align="center" colspan="1">BUFFERRDEN
                                <br>0x0</td>

                            <td align="center" colspan="1">BUFFERWREN
                                <br>0x0</td>

                            <td align="center" colspan="1">DMAINTEN
                                <br>0x0</td>

                            <td align="center" colspan="1">BLOCKGAPEN
                                <br>0x0</td>

                            <td align="center" colspan="1">XFERCMPEN
                                <br>0x0</td>

                            <td align="center" colspan="1">CMDCMPEN
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:29</td>
                            <td>VNDERREN</td>
                            <td>RW</td>
                            <td>VNDERREN field description needed here.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>28</td>
                            <td>TGTRESPEN</td>
                            <td>RW</td>
                            <td>Interrupt<br><br>
                                 MASKED               = 0x0 - Masked<br>
                             ENABLED              = 0x1 - Enabled</td>
                        </tr>

                        <tr>
                            <td>27</td>
                            <td>RSVD</td>
                            <td>RW</td>
                            <td>Desc<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>26</td>
                            <td>TUNINGERREN</td>
                            <td>RW</td>
                            <td>Desc<br><br>
                                 MASKED               = 0x0 - Masked<br>
                             ENABLED              = 0x1 - Enabled</td>
                        </tr>

                        <tr>
                            <td>25</td>
                            <td>ADMAERREN</td>
                            <td>RW</td>
                            <td>Desc<br><br>
                                 MASKED               = 0x0 - Masked<br>
                             ENABLED              = 0x1 - Enabled</td>
                        </tr>

                        <tr>
                            <td>24</td>
                            <td>AUTOCMD12ERREN</td>
                            <td>RW</td>
                            <td>Desc<br><br>
                                 MASKED               = 0x0 - Masked<br>
                             ENABLED              = 0x1 - Enabled</td>
                        </tr>

                        <tr>
                            <td>23</td>
                            <td>CURRLMTERREN</td>
                            <td>RW</td>
                            <td>Desc<br><br>
                                 MASKED               = 0x0 - Masked<br>
                             ENABLED              = 0x1 - Enabled</td>
                        </tr>

                        <tr>
                            <td>22</td>
                            <td>DATAENDERREN</td>
                            <td>RW</td>
                            <td>Desc<br><br>
                                 MASKED               = 0x0 - Masked<br>
                             ENABLED              = 0x1 - Enabled</td>
                        </tr>

                        <tr>
                            <td>21</td>
                            <td>DATACRCERREN</td>
                            <td>RW</td>
                            <td>Desc<br><br>
                                 MASKED               = 0x0 - Masked<br>
                             ENABLED              = 0x1 - Enabled</td>
                        </tr>

                        <tr>
                            <td>20</td>
                            <td>DATATOERROREN</td>
                            <td>RW</td>
                            <td>Desc<br><br>
                                 MASKED               = 0x0 - Masked<br>
                             ENABLED              = 0x1 - Enabled</td>
                        </tr>

                        <tr>
                            <td>19</td>
                            <td>CMDIDXERREN</td>
                            <td>RW</td>
                            <td>Desc<br><br>
                                 MASKED               = 0x0 - Masked<br>
                             ENABLED              = 0x1 - Enabled</td>
                        </tr>

                        <tr>
                            <td>18</td>
                            <td>CMDENDBITERREN</td>
                            <td>RW</td>
                            <td>Desc<br><br>
                                 MASKED               = 0x0 - Masked<br>
                             ENABLED              = 0x1 - Enabled</td>
                        </tr>

                        <tr>
                            <td>17</td>
                            <td>CMDCRCERREN</td>
                            <td>RW</td>
                            <td>Desc<br><br>
                                 MASKED               = 0x0 - Masked<br>
                             ENABLED              = 0x1 - Enabled</td>
                        </tr>

                        <tr>
                            <td>16</td>
                            <td>CMDTOERREN</td>
                            <td>RW</td>
                            <td>Desc<br><br>
                                 MASKED               = 0x0 - Masked<br>
                             ENABLED              = 0x1 - Enabled</td>
                        </tr>

                        <tr>
                            <td>15</td>
                            <td>FIXED0</td>
                            <td>RO</td>
                            <td>Fixed to 0. The HD shall control error Interrupts using the Error Interrupt Signal Enable register.<br><br>
                                 MASKED               = 0x0 - Masked<br>
                             ENABLED              = 0x1 - Enabled</td>
                        </tr>

                        <tr>
                            <td>14</td>
                            <td>BOOTTERM</td>
                            <td>RW</td>
                            <td>Boot terminate interrupt signal enable<br><br>
                                 MASKED               = 0x0 - Masked<br>
                             ENABLED              = 0x1 - Enabled</td>
                        </tr>

                        <tr>
                            <td>13</td>
                            <td>BOOTACKEN</td>
                            <td>RW</td>
                            <td>Interrupt<br><br>
                                 MASKED               = 0x0 - Masked<br>
                             ENABLED              = 0x1 - Enabled</td>
                        </tr>

                        <tr>
                            <td>12</td>
                            <td>RETUNEEVENTEN</td>
                            <td>RW</td>
                            <td>Interrupt signal enable<br><br>
                                 MASKED               = 0x0 - Masked<br>
                             ENABLED              = 0x1 - Enabled</td>
                        </tr>

                        <tr>
                            <td>11</td>
                            <td>INTCEN</td>
                            <td>RW</td>
                            <td>Interrupt<br><br>
                                 MASKED               = 0x0 - Masked<br>
                             ENABLED              = 0x1 - Enabled</td>
                        </tr>

                        <tr>
                            <td>10</td>
                            <td>INTBEN</td>
                            <td>RW</td>
                            <td>Interrupt<br><br>
                                 MASKED               = 0x0 - Masked<br>
                             ENABLED              = 0x1 - Enabled</td>
                        </tr>

                        <tr>
                            <td>9</td>
                            <td>INTAEN</td>
                            <td>RW</td>
                            <td>Interrupt<br><br>
                                 MASKED               = 0x0 - Masked<br>
                             ENABLED              = 0x1 - Enabled</td>
                        </tr>

                        <tr>
                            <td>8</td>
                            <td>CARDINTEN</td>
                            <td>RW</td>
                            <td>Interrupt<br><br>
                                 MASKED               = 0x0 - Masked<br>
                             ENABLED              = 0x1 - Enabled</td>
                        </tr>

                        <tr>
                            <td>7</td>
                            <td>CARDREMOVALEN</td>
                            <td>RW</td>
                            <td>Interrupt<br><br>
                                 MASKED               = 0x0 - Masked<br>
                             ENABLED              = 0x1 - Enabled</td>
                        </tr>

                        <tr>
                            <td>6</td>
                            <td>CARDINSERTEN</td>
                            <td>RW</td>
                            <td>Interrupt<br><br>
                                 MASKED               = 0x0 - Masked<br>
                             ENABLED              = 0x1 - Enabled</td>
                        </tr>

                        <tr>
                            <td>5</td>
                            <td>BUFFERRDEN</td>
                            <td>RW</td>
                            <td>Interrupt<br><br>
                                 MASKED               = 0x0 - Masked<br>
                             ENABLED              = 0x1 - Enabled</td>
                        </tr>

                        <tr>
                            <td>4</td>
                            <td>BUFFERWREN</td>
                            <td>RW</td>
                            <td>Interrupt<br><br>
                                 MASKED               = 0x0 - Masked<br>
                             ENABLED              = 0x1 - Enabled</td>
                        </tr>

                        <tr>
                            <td>3</td>
                            <td>DMAINTEN</td>
                            <td>RW</td>
                            <td>Interrupt<br><br>
                                 MASKED               = 0x0 - Masked<br>
                             ENABLED              = 0x1 - Enabled</td>
                        </tr>

                        <tr>
                            <td>2</td>
                            <td>BLOCKGAPEN</td>
                            <td>RW</td>
                            <td>Interrupt<br><br>
                                 MASKED               = 0x0 - Masked<br>
                             ENABLED              = 0x1 - Enabled</td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>XFERCMPEN</td>
                            <td>RW</td>
                            <td>Interrupt<br><br>
                                 MASKED               = 0x0 - Masked<br>
                             ENABLED              = 0x1 - Enabled</td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>CMDCMPEN</td>
                            <td>RW</td>
                            <td>Interrupt<br><br>
                                 MASKED               = 0x0 - Masked<br>
                             ENABLED              = 0x1 - Enabled</td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="AUTO" class="panel-title">AUTO - Auto CMD error status</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x4007003C</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Auto CMD error status</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="1">PRESETEN
                                <br>0x0</td>

                            <td align="center" colspan="1">ASYNCINTEN
                                <br>0x0</td>

                            <td align="center" colspan="6">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">SAMPLCLKSEL
                                <br>0x0</td>

                            <td align="center" colspan="1">STARTTUNING
                                <br>0x0</td>

                            <td align="center" colspan="2">DRVRSTRSEL
                                <br>0x0</td>

                            <td align="center" colspan="1">SIGNALVOLT
                                <br>0x0</td>

                            <td align="center" colspan="3">UHSMODESEL
                                <br>0x0</td>

                            <td align="center" colspan="8">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">NOTAUTOCMD12ERR
                                <br>0x0</td>

                            <td align="center" colspan="2">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">CMDIDXERR
                                <br>0x0</td>

                            <td align="center" colspan="1">CMDENDERR
                                <br>0x0</td>

                            <td align="center" colspan="1">CMDCRCERR
                                <br>0x0</td>

                            <td align="center" colspan="1">CMDTOERR
                                <br>0x0</td>

                            <td align="center" colspan="1">CMD12NOTEXEC
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31</td>
                            <td>PRESETEN</td>
                            <td>RW</td>
                            <td>Host Controller Version 3.00 supports this bit. As the operating SDCLK frequency and I/O driver strength depend on the Host System implementation, it is difficult to determine these parameters in the Standard Host Driver. When Preset Value Enable is set to automatic. This bit enables the functions defined in the Preset Value registers. If this bit is set to 0, SDCLK Frequency Select, Clock Generator Select in the Clock Control register and Driver Strength Select in Host Control 2 register are set by Host Driver. If this bit is set to 1, SDCLK Frequency Select, Clock Generator Select in the Clock Control register and Driver Strength Select in Host Control 2 register are set by Host Controller as specified in the Preset Value registers.<br><br>
                                 AUTOEN               = 0x1 - Automatic Selection by Preset Value are Enabled<br>
                             HOSTCTRL             = 0x0 - SDCLK and Driver Strength are controlled by Host Driver</td>
                        </tr>

                        <tr>
                            <td>30</td>
                            <td>ASYNCINTEN</td>
                            <td>RW</td>
                            <td>This bit can be set to 1 if a card support asynchronous interrupt and Asynchronous Interrupt Support is set to 1 in the Capabilities register. Asynchronous interrupt is effective when DAT[1] interrupt is used in 4-bit SD mode (and zero is set to Interrupt Pin Select in the Shared Bus Control register). If this bit is set to 1, the Host Driver can stop the SDCLK during asynchronous interrupt period to save power. During this period, the Host Controller continues to deliver Card Interrupt to the host when it is asserted by the Card.<br><br>
                                 ENABLED              = 0x1 - Enabled,<br>
                             DISABLED             = 0x0 - Disabled</td>
                        </tr>

                        <tr>
                            <td>29:24</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>23</td>
                            <td>SAMPLCLKSEL</td>
                            <td>RW</td>
                            <td>This bit is set by tuning procedure when Execute Tuning is cleared. Writing 1 to this bit is meaningless and ignored. Setting 1 means that tuning is completed successfully and setting 0 means that tuning is failed. Host Controller uses this bit to select sampling clock to receive CMD and DAT. This bit is cleared by writing 0. Change of this bit is not allowed while the Host Controller is receiving response or a read data block.<br><br>
                                 TUNEDCLK             = 0x1 - Tuned clock is used to sample data<br>
                             FIXEDCLK             = 0x0 - Fixed clock is used to sample data</td>
                        </tr>

                        <tr>
                            <td>22</td>
                            <td>STARTTUNING</td>
                            <td>RWAC</td>
                            <td>This bit is set to 1 to start tuning procedure and automatically cleared when tuning procedure is completed. The result of tuning is indicated to Sampling Clock Select. Tuning procedure is aborted by writing 0 for more detail about tuning procedure.<br><br>
                                 TUNESTART            = 0x1 - Execute Tuning,<br>
                             TUNECMP              = 0x0 - Not Tuned or Tuning Completed</td>
                        </tr>

                        <tr>
                            <td>21:20</td>
                            <td>DRVRSTRSEL</td>
                            <td>RW</td>
                            <td>Host Controller output driver in 1.8V signaling is selected by this bit. In 3.3V signaling, this field is not effective. This field can be set depends on Driver Type A, C and D support bits in the Capabilities register. This bit depends on setting of Preset Value Enable. If Preset Value Enable = 0, this field is set by Host Driver. If Preset Value Enable = 1, this field is automatically set by a value specified in the one of Preset Value registers.<br><br>
                                 DRVRB                = 0x0 - Driver Type B is Selected (Default)<br>
                             DRVRA                = 0x1 - Driver Type A is Selected<br>
                             DRVRC                = 0x2 - Driver Type C is Selected<br>
                             DRVRD                = 0x3 - Driver Type D is Selected</td>
                        </tr>

                        <tr>
                            <td>19</td>
                            <td>SIGNALVOLT</td>
                            <td>RW</td>
                            <td>This bit controls voltage regulator for I/O cell. 3.3V is supplied to the card regardless of signaling voltage. Setting this bit from 0 to 1 starts changing signal voltage from 3.3V to 1.8V. 1.8V regulator output shall be stable within 5ms. Host Controller clears this bit if switching to 1.8V signaling fails. Clearing this bit from 1 to 0 starts changing signal voltage from 1.8V to 3.3V. 3.3V regulator output shall be stable within 5ms. Host Driver can set this bit to 1 when Host Controller supports 1.8V signaling (One of support bits is set to 1: SDR50, SDR104 or DDR50 in the Capabilities register) and the card or device supports UHS-I<br><br>
                                 1_8V                 = 0x1 - 1.8V Signaling<br>
                             3_3V                 = 0x0 - 3.3V Signaling</td>
                        </tr>

                        <tr>
                            <td>18:16</td>
                            <td>UHSMODESEL</td>
                            <td>RW</td>
                            <td>This field is used to select one of UHS-I modes and effective when 1.8V Signaling Enable is set to 1. If Preset Value Enable in the Host Control 2 register is set to 1, Host Controller sets SDCLK Frequency Select, Clock Generator Select in the Clock Control register and Driver Strength Select according to Preset Value registers. In this case, one of preset value registers is selected by this field. Host Driver needs to reset SD Clock Enable before changing this field to avoid generating clock glitch. After setting this field, Host Driver sets SD Clock Enable again. When SDR50, SDR104 or DDR50 is selected for SDIO card, interrupt detection at the block gap shall not be used. Read Wait timing is changed for these modes. Refer to the SDIO Specification Version 3.00 for more detail.<br><br>
                                 SDR12                = 0x0 - UHS-I mode SDR12<br>
                             SDR25                = 0x1 - UHS-I mode SDR25<br>
                             SDR50                = 0x2 - UHS-I mode SDR50<br>
                             SDR104               = 0x3 - UHS-I mode SDR104<br>
                             DDR50                = 0x4 - UHS-I mode DDR50<br>
                             RSVD                 = 0x5 - 101b - 111b Reserved<br>
                             RSVD6                = 0x5 - 101b - 111b Reserved<br>
                             RSVD7                = 0x5 - 101b - 111b Reserved</td>
                        </tr>

                        <tr>
                            <td>15:8</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>7</td>
                            <td>NOTAUTOCMD12ERR</td>
                            <td>ROC</td>
                            <td>Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 error (D04 - D01) in this register. This bit is set to 0 when Auto CMD Error is generated by Auto CMD23<br><br>
                                 NOERROR              = 0x0 - No Error<br>
                             ERROR                = 0x1 - Not Issued</td>
                        </tr>

                        <tr>
                            <td>6:5</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>4</td>
                            <td>CMDIDXERR</td>
                            <td>ROC</td>
                            <td>Occurs if the Command Index error occurs in response to a command.<br><br>
                                 NOERROR              = 0x0 - No Error<br>
                             ERROR                = 0x1 - Error</td>
                        </tr>

                        <tr>
                            <td>3</td>
                            <td>CMDENDERR</td>
                            <td>ROC</td>
                            <td>Occurs when detecting that the end bit of command response is 0.<br><br>
                                 NOERROR              = 0x0 - No Error<br>
                             ERROR                = 0x1 - End Bit Error Generated</td>
                        </tr>

                        <tr>
                            <td>2</td>
                            <td>CMDCRCERR</td>
                            <td>ROC</td>
                            <td>Occurs when detecting a CRC error in the command response.<br><br>
                                 NOERROR              = 0x0 - No Error<br>
                             ERROR                = 0x1 - CRC Error Generated</td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>CMDTOERR</td>
                            <td>ROC</td>
                            <td>Occurs if the no response is returned within 64 SDCLK cycles from the end bit of the command. If this bit is set to 1, the other error status bits (D04 - D02) are meaningless.<br><br>
                                 NOERROR              = 0x0 - No Error<br>
                             ERROR                = 0x1 - Timeout</td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>CMD12NOTEXEC</td>
                            <td>ROC</td>
                            <td>If memory multiple block data transfer is not started due to command error, this bit is not set because it is not necessary to issue Auto CMD12. Setting this bit to 1 means the HC cannot issue Auto CMD12 to stop memory multiple block transfer due to some error. If this bit is set to 1, other error status bits (D04 - D01) are meaningless. This bit is set to 0 when Auto CMD Error is generated by Auto CMD23<br><br>
                                 EXECUTED             = 0x0 - Executed<br>
                             NOTEXECUTED          = 0x1 - Not Executed</td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="CAPABILITIES0" class="panel-title">CAPABILITIES0 - Capabilities</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40070040</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Capabilities</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="2">SLOTTYPE
                                <br>0x0</td>

                            <td align="center" colspan="1">ASYNCINT
                                <br>0x0</td>

                            <td align="center" colspan="1">SYSBUS64
                                <br>0x0</td>

                            <td align="center" colspan="1">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">VOLT18V
                                <br>0x0</td>

                            <td align="center" colspan="1">VOLT30V
                                <br>0x0</td>

                            <td align="center" colspan="1">VOLT33V
                                <br>0x0</td>

                            <td align="center" colspan="1">SUSPRES
                                <br>0x0</td>

                            <td align="center" colspan="1">SDMA
                                <br>0x0</td>

                            <td align="center" colspan="1">HIGHSPEED
                                <br>0x0</td>

                            <td align="center" colspan="1">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">ADMA2
                                <br>0x0</td>

                            <td align="center" colspan="1">EXTMEDIA
                                <br>0x0</td>

                            <td align="center" colspan="2">MAXBLKLEN
                                <br>0x0</td>

                            <td align="center" colspan="8">SDCLKFREQ
                                <br>0x0</td>

                            <td align="center" colspan="1">TOCLKUNIT
                                <br>0x0</td>

                            <td align="center" colspan="1">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="6">TOCLKFREQ
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:30</td>
                            <td>SLOTTYPE</td>
                            <td>RO</td>
                            <td>This field indicates usage of a slot by a specific Host System. (A host controller register set is defined per slot.) Embedded slot for one device (01b) means that only one non-removable device is connected to a SD bus slot. Shared Bus Slot (10b) can be set if Host Controller supports Shared Bus Control register. The Standard Host Driver controls only a removable card or one embedded device is connected to a SD bus slot. If a slot is configured for shared bus (10b), the Standard Host Driver does not control embedded devices connected to a shared bus. Shared bus slot is controlled by a specific host driver developed by a Host System.<br><br>
                                 REMOVABLE            = 0x0 - Removable card slot<br>
                             EMBEDDED             = 0x1 - Embedded Slot for One Device<br>
                             SHARED               = 0x2 - Shared Bus Slot<br>
                             RSVD                 = 0x3 - Reserved field.</td>
                        </tr>

                        <tr>
                            <td>29</td>
                            <td>ASYNCINT</td>
                            <td>RO</td>
                            <td>Refer to SDIO Specification Version 3.00 about asynchronous interrupt.<br><br>
                                 SUPPORTED            = 0x1 - Asynchronous Interrupt Supported<br>
                             NOTSUPPORTED         = 0x0 - Asynchronous Interrupt Not Supported</td>
                        </tr>

                        <tr>
                            <td>28</td>
                            <td>SYSBUS64</td>
                            <td>RO</td>
                            <td>Desc<br><br>
                                 SUPPORTED            = 0x1 - Supports 64 bit system address<br>
                             NOTSUPPORTED         = 0x0 - Does not support 64 bit system address</td>
                        </tr>

                        <tr>
                            <td>27</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Desc<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>26</td>
                            <td>VOLT18V</td>
                            <td>RO</td>
                            <td>Voltage support 1.8v<br><br>
                                 NOTSUPPORTED         = 0x0 - 1.8 V Not Supported<br>
                             SUPPORTED            = 0x1 - 1.8 V Supported</td>
                        </tr>

                        <tr>
                            <td>25</td>
                            <td>VOLT30V</td>
                            <td>RO</td>
                            <td>Voltage support 3.0v<br><br>
                                 NOTSUPPORTED         = 0x0 - 3.0 V Not Supported<br>
                             SUPPORTED            = 0x1 - 3.0 V Supported</td>
                        </tr>

                        <tr>
                            <td>24</td>
                            <td>VOLT33V</td>
                            <td>RO</td>
                            <td>Desc<br><br>
                                 NOTSUPPORTED         = 0x0 - 3.3 V Not Supported<br>
                             SUPPORTED            = 0x1 - 3.3 V Supported</td>
                        </tr>

                        <tr>
                            <td>23</td>
                            <td>SUSPRES</td>
                            <td>RO</td>
                            <td>This bit indicates whether the HC supports Suspend / Resume functionality. If this bit is 0, the Suspend and Resume mechanism are not supported and the HD shall not issue either Suspend / Resume commands.<br><br>
                                 NOTSUPPORTED         = 0x0 - Suspend / Resume Not Supported<br>
                             SUPPORTED            = 0x1 - Suspend / Resume Supported</td>
                        </tr>

                        <tr>
                            <td>22</td>
                            <td>SDMA</td>
                            <td>RO</td>
                            <td>This bit indicates whether the HC is capable of using DMA to transfer data between system memory and the HC directly.<br><br>
                                 NOTSUPPORTED         = 0x0 - SDMA Not Supported<br>
                             SUPPORTED            = 0x1 - SDMA Supported.</td>
                        </tr>

                        <tr>
                            <td>21</td>
                            <td>HIGHSPEED</td>
                            <td>RO</td>
                            <td>This bit indicates whether the HC and the Host System support High Speed mode and they can supply SD Clock frequency from 25Mhz to 50 Mhz (for SD)/ 20MHz to 52MHz (for MMC).<br><br>
                                 NOTSUPPORTED         = 0x0 - High Speed Not Supported<br>
                             SUPPORTED            = 0x1 - High Speed Supported</td>
                        </tr>

                        <tr>
                            <td>20</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>Desc<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>19</td>
                            <td>ADMA2</td>
                            <td>HwInit</td>
                            <td>Desc<br><br>
                                 SUPPORTED            = 0x1 - ADMA2 support.<br>
                             NOTSUPPORTED         = 0x0 - ADMA2 not support</td>
                        </tr>

                        <tr>
                            <td>18</td>
                            <td>EXTMEDIA</td>
                            <td>HwInit</td>
                            <td>This bit indicates whether the Host Controller is capable of using 8-bit bus width mode. This bit is not effective when Slot Type is set to 10b. In this case, refer to Bus Width Preset in the Shared Bus resister. Supported<br><br>
                                 SUPPORTED            = 0x1 - Extended Media Bus Supported<br>
                             NOTSUPPORTED         = 0x0 - Extended Media Bus not supported</td>
                        </tr>

                        <tr>
                            <td>17:16</td>
                            <td>MAXBLKLEN</td>
                            <td>HwInit</td>
                            <td>This value indicates the maximum block size that the HD can read and write to the buffer in the HC. The buffer shall transfer this block size without wait cycles. Three sizes can be defined as indicated below.<br><br>
                                 512                  = 0x0 - 512 byte<br>
                             1024                 = 0x1 - 1024 byte<br>
                             2048                 = 0x2 - 2048 byte<br>
                             4096                 = 0x3 - 4096 byte</td>
                        </tr>

                        <tr>
                            <td>15:8</td>
                            <td>SDCLKFREQ</td>
                            <td>HwInit</td>
                            <td>6-bit Base Clock Frequency This mode is supported by the Host Controller Version 1.00 and 2.00. Upper 2-bit is not effective and always 0. Unit values are 1MHz. The supported clock range is 10MHz to 63MHz. 11xx xxxxb Not supported 0011 1111b 63MHz 0000 0010b 2MHz 0000 0001b 1MHz 0000 0000b Get information via another method (2) 8-bit Base Clock Frequency This mode is supported by the Host Controller Version 3.00.Unit values are 1MHz. The supported clock range is 10MHz to 255MHz. FFh 255MHz 02h 2MHz 01h 1MHz 00h Get information via another method If the real frequency is 16.5MHz, the lager value shall be set 0001 0001b (17MHz) because the Host Driver use this value to calculate the clock divider value (Refer to the SDCLK Frequency Select in the Clock Control register.) and it shall not exceed upper limit of the SD Clock frequency. If these bits are all 0, the Host System has to get information via another method. Some example frequency values are enumerated below.<br><br>
                                 255MHZ               = 0xFF - 2) 8-bit base clock frequency supports frequencies 10MHz-255MHz.<br>
                             63MHZ                = 0x3F - 1) 6-bit base clock frequency supports frequencies 10MHz-63MHz. 2) 8-bit base clock frequency supports frequencies 10MHz-255MHz.<br>
                             2MHZ                 = 0x2 - 1) 6-bit base clock frequency supports frequencies 10MHz-63MHz. 2) 8-bit base clock frequency supports frequencies 10MHz-255MHz.<br>
                             1MHZ                 = 0x1 - 1) 6-bit base clock frequency supports frequencies 10MHz-63MHz. 2) 8-bit base clock frequency supports frequencies 10MHz-255MHz.<br>
                             OTHER                = 0x0 - Get information via another method</td>
                        </tr>

                        <tr>
                            <td>7</td>
                            <td>TOCLKUNIT</td>
                            <td>HwInit</td>
                            <td>This bit shows the unit of base clock frequency used to detect Data Timeout Error.<br><br>
                                 KHZ                  = 0x0 - Khz<br>
                             MHZ                  = 0x1 - Mhz</td>
                        </tr>

                        <tr>
                            <td>6</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>5:0</td>
                            <td>TOCLKFREQ</td>
                            <td>HwInit</td>
                            <td>This bit shows the base clock frequency used to detect Data Timeout Error. Not 0 - 1Khz to 63Khz or 1Mhz to 63Mhz Note: The Host System shall support at least one of these voltages above. The HD sets the SD Bus Voltage Select in Power Control register according to these support bits. If multiple voltages are supported, select the usable lower voltage by comparing the OCR value from the card. These registers indicate maximum current capability for each voltage. The value is meaningful if Voltage Support is set in the Capabilities register.<br><br>
                                 1                    = 0x1 - 1KHZ or 1MHZ<br>
                             2                    = 0x2 - 2KHZ or 2MHZ<br>
                             63                   = 0x3F - 63KHZ or 63MHZ<br>
                             OTHER                = 0x0 - Get Information via another method.</td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="CAPABILITIES1" class="panel-title">CAPABILITIES1 - Capabilities</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40070044</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Capabilities</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="6">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">SPIBLOCKMODE
                                <br>0x0</td>

                            <td align="center" colspan="1">SPIMODE
                                <br>0x0</td>

                            <td align="center" colspan="8">CLKMULT
                                <br>0x0</td>

                            <td align="center" colspan="2">RETUNINGMODES
                                <br>0x0</td>

                            <td align="center" colspan="1">TUNINGSDR50
                                <br>0x0</td>

                            <td align="center" colspan="1">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="4">RETUNINGTMRCNT
                                <br>0x0</td>

                            <td align="center" colspan="1">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">TYPED
                                <br>0x0</td>

                            <td align="center" colspan="1">TYPEC
                                <br>0x0</td>

                            <td align="center" colspan="1">TYPEA
                                <br>0x0</td>

                            <td align="center" colspan="1">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">DDR50
                                <br>0x0</td>

                            <td align="center" colspan="1">SDR104
                                <br>0x0</td>

                            <td align="center" colspan="1">SDR50
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:26</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>25</td>
                            <td>SPIBLOCKMODE</td>
                            <td>RO</td>
                            <td>Spi block mode<br><br>
                                 NOTSUPPORTED         = 0x0 - Not Supported<br>
                             SUPPORTED            = 0x1 - Supported</td>
                        </tr>

                        <tr>
                            <td>24</td>
                            <td>SPIMODE</td>
                            <td>RO</td>
                            <td>Spi mode<br><br>
                                 NOTSUPPORTED         = 0x0 - Not Supported<br>
                             SUPPORTED            = 0x1 - Supported</td>
                        </tr>

                        <tr>
                            <td>23:16</td>
                            <td>CLKMULT</td>
                            <td>RO</td>
                            <td>This field indicates clock multiplier value of programmable clock generator. Refer to Clock Control register. Setting 00h means that Host Controller does not support programmable clock generator. The multiplier is (CLKMULT+1).<br><br>
                                 MULTX256             = 0xFF - Clock Multiplier M = 256<br>
                             MULTX3               = 0x2 - Clock Multiplier M = 3<br>
                             MULTX2               = 0x1 - Clock Multiplier M = 2<br>
                             NOTSUPPORTED         = 0x0 - Clock Multiplier is Not Supported</td>
                        </tr>

                        <tr>
                            <td>15:14</td>
                            <td>RETUNINGMODES</td>
                            <td>RO</td>
                            <td>This field defines the re-tuning capability of a Host Controller and how to manage the data transfer length and a Re-Tuning Timer by the Host Driver There are two re-tuning timings: Re-Tuning Request and expiration of a Re-Tuning Timer. By receiving either timing, the Host Driver executes the re-tuning procedure just before a next command issue<br><br>
                                 MODE1                = 0x0 - Mode1<br>
                             MODE2                = 0x1 - Mode2<br>
                             MODE3                = 0x2 - Mode3<br>
                             NOTSUPPORTED         = 0x3 - Clock Multiplier is not supported.</td>
                        </tr>

                        <tr>
                            <td>13</td>
                            <td>TUNINGSDR50</td>
                            <td>RO</td>
                            <td>If this bit is set to 1, this Host Controller requires tuning to operate SDR50. (Tuning is always required to operate SDR104.)<br><br>
                                 TUNINGREQD           = 0x1 - SDR50 requires tuning<br>
                             NOTUNINGREQD         = 0x0 - SDR50 does not require tuning</td>
                        </tr>

                        <tr>
                            <td>12</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Desc<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>11:8</td>
                            <td>RETUNINGTMRCNT</td>
                            <td>RO</td>
                            <td>This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3. 0h - Get information via other source.<br><br>
                                 OTHER                = 0x0 - 0h Get information via other source.<br>
                             1SEC                 = 0x1 - 1 seconds<br>
                             2SEC                 = 0x2 - 2 seconds<br>
                             4SEC                 = 0x3 - 4 seconds<br>
                             8S                   = 0x4 - 8 seconds<br>
                             16S                  = 0x5 - 16 seconds<br>
                             32S                  = 0x6 - 32 seconds<br>
                             64S                  = 0x7 - 64 seconds<br>
                             128S                 = 0x8 - 128 seconds<br>
                             256S                 = 0x9 - 256 seconds<br>
                             512S                 = 0xA - 512 seconds<br>
                             1024S                = 0xB - 1024 seconds<br>
                             RSVDC                = 0xC - 0xC - 0xF = Reserved (not valid)<br>
                             RSVDD                = 0xD - 0xC - 0xF = Reserved (not valid)<br>
                             RSVDE                = 0xE - 0xC - 0xF = Reserved (not valid)<br>
                             RSVDF                = 0xF - 0xC - 0xF = Reserved (not valid)</td>
                        </tr>

                        <tr>
                            <td>7</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>6</td>
                            <td>TYPED</td>
                            <td>RO</td>
                            <td>Reserved This bit indicates support of Driver Type D for 1.8 Signaling.<br><br>
                                 SUPPORTED            = 0x1 - Driver Type D is Supported<br>
                             NOTSUPPORTED         = 0x0 - Driver Type D is Not Supported</td>
                        </tr>

                        <tr>
                            <td>5</td>
                            <td>TYPEC</td>
                            <td>RO</td>
                            <td>This bit indicates support of Driver Type C for 1.8 Signaling.<br><br>
                                 SUPPORTED            = 0x1 - Driver Type C is Supported<br>
                             NOTSUPPORTED         = 0x0 - Driver Type C is Not Supported</td>
                        </tr>

                        <tr>
                            <td>4</td>
                            <td>TYPEA</td>
                            <td>RO</td>
                            <td>This bit indicates support of Driver Type A for 1.8 Signaling.<br><br>
                                 SUPPORTED            = 0x1 - Driver Type A is Supported<br>
                             NOTSUPPORTED         = 0x0 - Driver Type A is Not Supported</td>
                        </tr>

                        <tr>
                            <td>3</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>2</td>
                            <td>DDR50</td>
                            <td>RO</td>
                            <td>DDR50 field description needed here.<br><br>
                                 SUPPORTED            = 0x1 - DDR50 is Supported<br>
                             NOTSUPPORTED         = 0x0 - DDR50 is Not Supported</td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>SDR104</td>
                            <td>RO</td>
                            <td>1- SDR104 is Supported<br><br>
                                 SUPPORTED            = 0x1 - SDR104 is Not Supported<br>
                             NOTSUPPORTED         = 0x0 - SDR104 is Not Supported</td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>SDR50</td>
                            <td>RO</td>
                            <td>1- SDR50 is Supported<br><br>
                                 SUPPORTED            = 0x1 - SDR50 is Not Supported<br>
                             NOTSUPPORTED         = 0x0 - SDR50 is Not Supported</td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="MAXIMUM0" class="panel-title">MAXIMUM0 - Maximum current capabilities</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40070048</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Maximum current capabilities</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="32">ALLBITSRSVD
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:0</td>
                            <td>ALLBITSRSVD</td>
                            <td>Rsvd</td>
                            <td>The entire 32-bits of this register are reserved, do not read or write.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="MAXIMUM1" class="panel-title">MAXIMUM1 - Maximum current capabilities</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x4007004C</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Maximum current capabilities</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="8">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="8">MAXCURR18V
                                <br>0x0</td>

                            <td align="center" colspan="8">MAXCURR30V
                                <br>0x0</td>

                            <td align="center" colspan="8">MAXCURR33V
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:24</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>23:16</td>
                            <td>MAXCURR18V</td>
                            <td>HwInit</td>
                            <td>Maximum Current for 1.8V. The current value is specified as MAXCURR18V * 4mA. Some example enums follow:<br><br>
                                 1020mA               = 0xFF - 1020mA = 255 * 4mA<br>
                             4mA                  = 0x1 - 1020mA, 255 * 4mA<br>
                             OTHER                = 0x1 - Get information via another method</td>
                        </tr>

                        <tr>
                            <td>15:8</td>
                            <td>MAXCURR30V</td>
                            <td>HwInit</td>
                            <td>Maximum Current for 3.0V. The current value is specified as MAXCURR18V * 4mA. Some example enums follow:<br><br>
                                 1020mA               = 0xFF - 1020mA = 255 * 4mA<br>
                             4mA                  = 0x1 - 1020mA, 255 * 4mA<br>
                             OTHER                = 0x1 - Get information via another method</td>
                        </tr>

                        <tr>
                            <td>7:0</td>
                            <td>MAXCURR33V</td>
                            <td>HwInit</td>
                            <td>Maximum Current for 3.3V. The current value is specified as MAXCURR18V * 4mA. Some example enums follow:<br><br>
                                 1020mA               = 0xFF - 1020mA = 255 * 4mA<br>
                             4mA                  = 0x1 - 1020mA, 255 * 4mA<br>
                             OTHER                = 0x1 - Get information via another method</td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="FORCE" class="panel-title">FORCE - Force event register for error interrupt status</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40070050</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Force event register for error interrupt status</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="6">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">FORCEADMAERR
                                <br>0x0</td>

                            <td align="center" colspan="1">FORCEACMDERR
                                <br>0x0</td>

                            <td align="center" colspan="1">FORCECURRLIMITERR
                                <br>0x0</td>

                            <td align="center" colspan="1">FORCEDATAENDERR
                                <br>0x0</td>

                            <td align="center" colspan="1">FORCEDATACRCERR
                                <br>0x0</td>

                            <td align="center" colspan="1">FORCEDATATOERR
                                <br>0x0</td>

                            <td align="center" colspan="1">FORCECMDIDXERR
                                <br>0x0</td>

                            <td align="center" colspan="1">FORCECMDENDERR
                                <br>0x0</td>

                            <td align="center" colspan="1">FORCECMDCRCERR
                                <br>0x0</td>

                            <td align="center" colspan="1">FORCECMDTOERR
                                <br>0x0</td>

                            <td align="center" colspan="8">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">FORCEACMDISSUEDERR
                                <br>0x0</td>

                            <td align="center" colspan="2">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">FORCEACMDIDXERR
                                <br>0x0</td>

                            <td align="center" colspan="1">FORCEACMDENDERR
                                <br>0x0</td>

                            <td align="center" colspan="1">FORCEACMDCRCERR
                                <br>0x0</td>

                            <td align="center" colspan="1">FORCEACMDTOERR
                                <br>0x0</td>

                            <td align="center" colspan="1">FORCEACMD12NOT
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:26</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Rsvd<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>25</td>
                            <td>FORCEADMAERR</td>
                            <td>WO</td>
                            <td>Force event for ADMA error<br><br>
                                 INT                  = 0x1 - Interrupt is generated<br>
                             NOINT                = 0x0 - No interrupt</td>
                        </tr>

                        <tr>
                            <td>24</td>
                            <td>FORCEACMDERR</td>
                            <td>WO</td>
                            <td>Force Event for Auto CMD Error<br><br>
                                 INT                  = 0x1 - Interrupt is generated<br>
                             NOINT                = 0x0 - No interrupt</td>
                        </tr>

                        <tr>
                            <td>23</td>
                            <td>FORCECURRLIMITERR</td>
                            <td>WO</td>
                            <td>Force Event for Current Limit Error<br><br>
                                 INT                  = 0x1 - Interrupt is generated<br>
                             NOINT                = 0x0 - No interrupt</td>
                        </tr>

                        <tr>
                            <td>22</td>
                            <td>FORCEDATAENDERR</td>
                            <td>WO</td>
                            <td>Force Event for Data End Bit Error<br><br>
                                 INT                  = 0x1 - Interrupt is generated<br>
                             NOINT                = 0x0 - No interrupt</td>
                        </tr>

                        <tr>
                            <td>21</td>
                            <td>FORCEDATACRCERR</td>
                            <td>WO</td>
                            <td>Force Event for Data CRC Error<br><br>
                                 INT                  = 0x1 - Interrupt is generated<br>
                             NOINT                = 0x0 - No interrupt</td>
                        </tr>

                        <tr>
                            <td>20</td>
                            <td>FORCEDATATOERR</td>
                            <td>WO</td>
                            <td>Force Event for Data Timeout Error<br><br>
                                 INT                  = 0x1 - Interrupt is generated<br>
                             NOINT                = 0x0 - No interrupt</td>
                        </tr>

                        <tr>
                            <td>19</td>
                            <td>FORCECMDIDXERR</td>
                            <td>WO</td>
                            <td>Force Event for Command Index Error<br><br>
                                 INT                  = 0x1 - Interrupt is generated<br>
                             NOINT                = 0x0 - No interrupt</td>
                        </tr>

                        <tr>
                            <td>18</td>
                            <td>FORCECMDENDERR</td>
                            <td>WO</td>
                            <td>Force Event for Command End Bit Error<br><br>
                                 INT                  = 0x1 - Interrupt is generated<br>
                             NOINT                = 0x0 - No interrupt</td>
                        </tr>

                        <tr>
                            <td>17</td>
                            <td>FORCECMDCRCERR</td>
                            <td>WO</td>
                            <td>Force Event for Command CRC Error<br><br>
                                 INT                  = 0x1 - Interrupt is generated<br>
                             NOINT                = 0x0 - No interrupt</td>
                        </tr>

                        <tr>
                            <td>16</td>
                            <td>FORCECMDTOERR</td>
                            <td>WO</td>
                            <td>Force Event for Command Timeout Error<br><br>
                                 INT                  = 0x1 - Interrupt is generated<br>
                             NOINT                = 0x0 - No interrupt</td>
                        </tr>

                        <tr>
                            <td>15:8</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>7</td>
                            <td>FORCEACMDISSUEDERR</td>
                            <td>WO</td>
                            <td>1 - Interrupt is generated<br><br>
                                 INT                  = 0x1 - Interrupt is generated<br>
                             NOINT                = 0x0 - no interrupt</td>
                        </tr>

                        <tr>
                            <td>6:5</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>4</td>
                            <td>FORCEACMDIDXERR</td>
                            <td>WO</td>
                            <td>Desc<br><br>
                                 INT                  = 0x1 - Interrupt is generated<br>
                             NOINT                = 0x0 - no interrupt</td>
                        </tr>

                        <tr>
                            <td>3</td>
                            <td>FORCEACMDENDERR</td>
                            <td>WO</td>
                            <td>Description<br><br>
                                 INT                  = 0x1 - Interrupt is generated<br>
                             NOINT                = 0x0 - no interrupt</td>
                        </tr>

                        <tr>
                            <td>2</td>
                            <td>FORCEACMDCRCERR</td>
                            <td>WO</td>
                            <td>Description<br><br>
                                 INT                  = 0x1 - Interrupt is generated<br>
                             NOINT                = 0x0 - no interrupt</td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>FORCEACMDTOERR</td>
                            <td>WO</td>
                            <td>Description<br><br>
                                 INT                  = 0x1 - Interrupt is generated<br>
                             NOINT                = 0x0 - no interrupt</td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>FORCEACMD12NOT</td>
                            <td>WO</td>
                            <td>Description<br><br>
                                 INT                  = 0x1 - Interrupt is generated<br>
                             NOINT                = 0x0 - no interrupt</td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="ADMA" class="panel-title">ADMA - ADMA error status</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40070054</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>ADMA error status</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="29">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">ADMALENMISMATCHERR
                                <br>0x0</td>

                            <td align="center" colspan="2">ADMAERRORSTATE
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:3</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>2</td>
                            <td>ADMALENMISMATCHERR</td>
                            <td>RO</td>
                            <td>This error occurs in the following 2 cases. While Block Count Enable being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length. Total data length can not be divided by the block length.<br><br>
                                 ERROR                = 0x1 - Error<br>
                             NOERROR              = 0x0 - No error</td>
                        </tr>

                        <tr>
                            <td>1:0</td>
                            <td>ADMAERRORSTATE</td>
                            <td>RO</td>
                            <td>This field indicates the state of ADMA when error is occurred during ADMA data transfer. This field never indicates 10 because ADMA never stops in this state. D01 - D00 : ADMA Error State when error occurred Contents of SYS_SDR register<br><br>
                                 STDMA                = 0x0 - ST_STOP (Stop DMA) Points to next of the error descriptor<br>
                             FETCHDESC            = 0x1 - ST_FDS (Fetch Descriptor) Points to the error descriptor<br>
                             INVALID              = 0x2 - Never set this state (Not used)<br>
                             XFERDATA             = 0x3 - ST_TFR (Transfer Data) Points to the next of the error descriptor</td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="ADMALOWD" class="panel-title">ADMALOWD - ADMA system address [31:0]</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40070058</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>ADMA system address [31:0]</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="32">LOWD
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:0</td>
                            <td>LOWD</td>
                            <td>RW</td>
                            <td>This register holds byte address of executing command of the Descriptor table. 32-bit Address Descriptor uses lower 32bit of this register. At the start of ADMA, the Host Driver shall set start address of the Descriptor table. The ADMA increments this register address, which points to next line, when every fetching a Descriptor line. When the ADMA Error Interrupt is generated, this register shall hold valid Descriptor address depending on the ADMA state. The Host Driver shall program Descriptor Table on 32-bit boundary and set 32-bit boundary address to this register. ADMA2 ignores lower 2-bit of this register and assumes it to be 00b. 32-bit Address ADMA Register Value 32bit System Address<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="ADMAHIWD" class="panel-title">ADMAHIWD - ADMA system address [63:0]</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x4007005C</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>ADMA system address [63:0]</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="32">HIWD
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:0</td>
                            <td>HIWD</td>
                            <td>RW</td>
                            <td>This register holds byte address of executing command of the Descriptor table. 32-bit Address Descriptor uses lower 32bit of this register. At the start of ADMA, the Host Driver shall set start address of the Descriptor table. The ADMA increments this register address, which points to next line, when every fetching a Descriptor line. When the ADMA Error Interrupt is generated, this register shall hold valid Descriptor address depending on the ADMA state. The Host Driver shall program Descriptor Table on 32-bit boundary and set 32-bit boundary address to this register. ADMA2 ignores lower 2-bit of this register and assumes it to be 00b. 32-bit Address ADMA Register Value 32bit System Address<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="PRESET0" class="panel-title">PRESET0 - Preset Value initialization and default speed</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40070060</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Preset Value initialization and default speed</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="2">DEFSPDRVRSTRSEL
                                <br>0x0</td>

                            <td align="center" colspan="3">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">DEFSPCLKGENSEL
                                <br>0x0</td>

                            <td align="center" colspan="10">DEFSPSDCLKFREQSEL
                                <br>0x0</td>

                            <td align="center" colspan="2">HISPDRVRSTRSEL
                                <br>0x0</td>

                            <td align="center" colspan="3">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">HISPCLKGENSEL
                                <br>0x0</td>

                            <td align="center" colspan="10">HISPSDCLKFREQSEL
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:30</td>
                            <td>DEFSPDRVRSTRSEL</td>
                            <td>Hwinit</td>
                            <td>Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling.<br><br>
                                 TYPED                = 0x3 - Driver Type D is Selected<br>
                             TYPEC                = 0x2 - Driver Type C is Selected<br>
                             TYPEA                = 0x1 - Driver Type A is Selected<br>
                             TYPEB                = 0x0 - Driver Type B is Selected</td>
                        </tr>

                        <tr>
                            <td>29:27</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>26</td>
                            <td>DEFSPCLKGENSEL</td>
                            <td>Hwinit</td>
                            <td>This bit is effective when Host Controller supports programmable clock generator.<br><br>
                                 PROGCLK              = 0x1 - Programmable Clock Generator<br>
                             HOSTCTLR             = 0x0 - Host Controller Ver2.00 Compatible Clock Generator</td>
                        </tr>

                        <tr>
                            <td>25:16</td>
                            <td>DEFSPSDCLKFREQSEL</td>
                            <td>Hwinit</td>
                            <td>10 bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system. When Host Controller supports shared bus, a set of Preset Value registers for each device required and the registers location are duplicated to the offset 06Fh-060h. A set of Preset Value registers can be accessible by selecting Clock Pin Select in the Shared Bus Control register<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>15:14</td>
                            <td>HISPDRVRSTRSEL</td>
                            <td>Hwinit</td>
                            <td>Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling.<br><br>
                                 TYPED                = 0x3 - Driver Type D is Selected<br>
                             TYPEC                = 0x2 - Driver Type C is Selected<br>
                             TYPEA                = 0x1 - Driver Type A is Selected<br>
                             TYPEB                = 0x0 - Driver Type B is Selected</td>
                        </tr>

                        <tr>
                            <td>13:11</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>10</td>
                            <td>HISPCLKGENSEL</td>
                            <td>Hwinit</td>
                            <td>This bit is effective when Host Controller supports programmable clock generator.<br><br>
                                 PROGCLK              = 0x1 - Programmable Clock Generator<br>
                             HOSTCTLR             = 0x0 - Host Controller Ver2.00 Compatible Clock Generator</td>
                        </tr>

                        <tr>
                            <td>9:0</td>
                            <td>HISPSDCLKFREQSEL</td>
                            <td>Hwinit</td>
                            <td>10 bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system. When Host Controller supports shared bus, a set of Preset Value registers for each device required and the registers location are duplicated to the offset 06Fh-060h. A set of Preset Value registers can be accessible by selecting Clock Pin Select in the Shared Bus Control register<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="PRESET1" class="panel-title">PRESET1 - Preset Value for high speed and SDR12</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40070064</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Preset Value for high speed and SDR12</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="2">SDR12DRVRSTRSEL
                                <br>0x0</td>

                            <td align="center" colspan="3">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">SDR12CLKGENSEL
                                <br>0x0</td>

                            <td align="center" colspan="10">SDR12SDCLKFREQSEL
                                <br>0x0</td>

                            <td align="center" colspan="2">HSDRVRSTRSEL
                                <br>0x0</td>

                            <td align="center" colspan="3">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">HSCLKGENSEL
                                <br>0x0</td>

                            <td align="center" colspan="10">HSSDCLKFREQSEL
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:30</td>
                            <td>SDR12DRVRSTRSEL</td>
                            <td>Hwinit</td>
                            <td>Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling.<br><br>
                                 TYPED                = 0x3 - Driver Type D is Selected<br>
                             TYPEC                = 0x2 - Driver Type C is Selected<br>
                             TYPEA                = 0x1 - Driver Type A is Selected<br>
                             TYPEB                = 0x0 - Driver Type B is Selected</td>
                        </tr>

                        <tr>
                            <td>29:27</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>26</td>
                            <td>SDR12CLKGENSEL</td>
                            <td>Hwinit</td>
                            <td>This bit is effective when Host Controller supports programmable clock generator.<br><br>
                                 PROGCLK              = 0x1 - Programmable Clock Generator<br>
                             HOSTCTLR             = 0x0 - Host Controller Ver2.00 Compatible Clock Generator</td>
                        </tr>

                        <tr>
                            <td>25:16</td>
                            <td>SDR12SDCLKFREQSEL</td>
                            <td>Hwinit</td>
                            <td>10 bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system. When Host Controller supports shared bus, a set of Preset Value registers for each device required and the registers location are duplicated to the offset 06Fh-060h. A set of Preset Value registers can be accessible by selecting Clock Pin Select in the Shared Bus Control register<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>15:14</td>
                            <td>HSDRVRSTRSEL</td>
                            <td>Hwinit</td>
                            <td>Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling.<br><br>
                                 TYPED                = 0x3 - Driver Type D is Selected<br>
                             TYPEC                = 0x2 - Driver Type C is Selected<br>
                             TYPEA                = 0x1 - Driver Type A is Selected<br>
                             TYPEB                = 0x0 - Driver Type B is Selected</td>
                        </tr>

                        <tr>
                            <td>13:11</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>10</td>
                            <td>HSCLKGENSEL</td>
                            <td>Hwinit</td>
                            <td>This bit is effective when Host Controller supports programmable clock generator.<br><br>
                                 PROGCLK              = 0x1 - Programmable Clock Generator<br>
                             HOSTCTLR             = 0x0 - Host Controller Ver2.00 Compatible Clock Generator</td>
                        </tr>

                        <tr>
                            <td>9:0</td>
                            <td>HSSDCLKFREQSEL</td>
                            <td>Hwinit</td>
                            <td>10 bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system. When Host Controller supports shared bus, a set of Preset Value registers for each device required and the registers location are duplicated to the offset 06Fh-060h. A set of Preset Value registers can be accessible by selecting Clock Pin Select in the Shared Bus Control register<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="PRESET2" class="panel-title">PRESET2 - Preset Value for SDR25 and SDR50</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40070068</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Preset Value for SDR25 and SDR50</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="2">SDR50DRVRSTRSEL
                                <br>0x0</td>

                            <td align="center" colspan="3">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">SDR50CLKGENSEL
                                <br>0x0</td>

                            <td align="center" colspan="10">SDR50SDCLKFREQSEL
                                <br>0x0</td>

                            <td align="center" colspan="2">SDR25DRVRSTRSEL
                                <br>0x0</td>

                            <td align="center" colspan="3">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">SDR25CLKGENSEL
                                <br>0x0</td>

                            <td align="center" colspan="10">SDR25SDCLKFREQSEL
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:30</td>
                            <td>SDR50DRVRSTRSEL</td>
                            <td>Hwinit</td>
                            <td>Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling.<br><br>
                                 TYPED                = 0x3 - Driver Type D is Selected<br>
                             TYPEC                = 0x2 - Driver Type C is Selected<br>
                             TYPEA                = 0x1 - Driver Type A is Selected<br>
                             TYPEB                = 0x0 - Driver Type B is Selected</td>
                        </tr>

                        <tr>
                            <td>29:27</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>26</td>
                            <td>SDR50CLKGENSEL</td>
                            <td>Hwinit</td>
                            <td>This bit is effective when Host Controller supports programmable clock generator.<br><br>
                                 PROGCLK              = 0x1 - Programmable Clock Generator<br>
                             HOSTCTLR             = 0x0 - Host Controller Ver2.00 Compatible Clock Generator</td>
                        </tr>

                        <tr>
                            <td>25:16</td>
                            <td>SDR50SDCLKFREQSEL</td>
                            <td>Hwinit</td>
                            <td>10 bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system. When Host Controller supports shared bus, a set of Preset Value registers for each device required and the registers location are duplicated to the offset 06Fh-060h. A set of Preset Value registers can be accessible by selecting Clock Pin Select in the Shared Bus Control register<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>15:14</td>
                            <td>SDR25DRVRSTRSEL</td>
                            <td>Hwinit</td>
                            <td>Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling.<br><br>
                                 TYPED                = 0x3 - Driver Type D is Selected<br>
                             TYPEC                = 0x2 - Driver Type C is Selected<br>
                             TYPEA                = 0x1 - Driver Type A is Selected<br>
                             TYPEB                = 0x0 - Driver Type B is Selected</td>
                        </tr>

                        <tr>
                            <td>13:11</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>10</td>
                            <td>SDR25CLKGENSEL</td>
                            <td>Hwinit</td>
                            <td>This bit is effective when Host Controller supports programmable clock generator.<br><br>
                                 PROGCLK              = 0x1 - Programmable Clock Generator<br>
                             HOSTCTLR             = 0x0 - Host Controller Ver2.00 Compatible Clock Generator</td>
                        </tr>

                        <tr>
                            <td>9:0</td>
                            <td>SDR25SDCLKFREQSEL</td>
                            <td>Hwinit</td>
                            <td>10 bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system. When Host Controller supports shared bus, a set of Preset Value registers for each device required and the registers location are duplicated to the offset 06Fh-060h. A set of Preset Value registers can be accessible by selecting Clock Pin Select in the Shared Bus Control register<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="PRESET3" class="panel-title">PRESET3 - Preset Value for SDR104 and DDR50</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x4007006C</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Preset Value for SDR104 and DDR50</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="2">DDR50DRVRSTRSEL
                                <br>0x0</td>

                            <td align="center" colspan="3">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">DDR50CLKGENSEL
                                <br>0x0</td>

                            <td align="center" colspan="10">DDR50SDCLKFREQSEL
                                <br>0x0</td>

                            <td align="center" colspan="2">SDR104DRVRSTRSEL
                                <br>0x0</td>

                            <td align="center" colspan="3">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">SDR104CLKGENSEL
                                <br>0x0</td>

                            <td align="center" colspan="10">SDR104SDCLKFREQSEL
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:30</td>
                            <td>DDR50DRVRSTRSEL</td>
                            <td>Hwinit</td>
                            <td>Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling.<br><br>
                                 TYPED                = 0x3 - Driver Type D is Selected<br>
                             TYPEC                = 0x2 - Driver Type C is Selected<br>
                             TYPEA                = 0x1 - Driver Type A is Selected<br>
                             TYPEB                = 0x0 - Driver Type B is Selected</td>
                        </tr>

                        <tr>
                            <td>29:27</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>26</td>
                            <td>DDR50CLKGENSEL</td>
                            <td>Hwinit</td>
                            <td>This bit is effective when Host Controller supports programmable clock generator.<br><br>
                                 PROGCLK              = 0x1 - Programmable Clock Generator<br>
                             HOSTCTLR             = 0x0 - Host Controller Ver2.00 Compatible Clock Generator</td>
                        </tr>

                        <tr>
                            <td>25:16</td>
                            <td>DDR50SDCLKFREQSEL</td>
                            <td>Hwinit</td>
                            <td>10 bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system. When Host Controller supports shared bus, a set of Preset Value registers for each device required and the registers location are duplicated to the offset 06Fh-060h. A set of Preset Value registers can be accessible by selecting Clock Pin Select in the Shared Bus Control register<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>15:14</td>
                            <td>SDR104DRVRSTRSEL</td>
                            <td>Hwinit</td>
                            <td>Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling.<br><br>
                                 TYPED                = 0x3 - Driver Type D is Selected<br>
                             TYPEC                = 0x2 - Driver Type C is Selected<br>
                             TYPEA                = 0x1 - Driver Type A is Selected<br>
                             TYPEB                = 0x0 - Driver Type B is Selected</td>
                        </tr>

                        <tr>
                            <td>13:11</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>10</td>
                            <td>SDR104CLKGENSEL</td>
                            <td>Hwinit</td>
                            <td>This bit is effective when Host Controller supports programmable clock generator.<br><br>
                                 PROGCLK              = 0x1 - Programmable Clock Generator<br>
                             HOSTCTLR             = 0x0 - Host Controller Ver2.00 Compatible Clock Generator</td>
                        </tr>

                        <tr>
                            <td>9:0</td>
                            <td>SDR104SDCLKFREQSEL</td>
                            <td>Hwinit</td>
                            <td>10 bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system. When Host Controller supports shared bus, a set of Preset Value registers for each device required and the registers location are duplicated to the offset 06Fh-060h. A set of Preset Value registers can be accessible by selecting Clock Pin Select in the Shared Bus Control register<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="BOOTTOCTRL" class="panel-title">BOOTTOCTRL - Boot Data Timeout control</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40070070</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Boot Data Timeout control</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="32">BOOTDATATO
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:0</td>
                            <td>BOOTDATATO</td>
                            <td>RW</td>
                            <td>This value determines the interval by which DAT line time-outs are detected during boot operation for eMMC card. The value is in number of sd clock.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="VENDOR" class="panel-title">VENDOR - Vendor</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40070078</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Vendor</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="30">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">DLYDIS
                                <br>0x0</td>

                            <td align="center" colspan="1">GATESDCLKEN
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:2</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>DLYDIS</td>
                            <td>RW</td>
                            <td>Chicken bit added to enable/disable the rtl fix made to delay the sampling of cmd_in and data_in.<br><br>
                                 DISABLE              = 0x1 - Disable the rtl fix made to delay the sampling of cmd_in and data_in<br>
                             ENABLE               = 0x0 - Enable the rtl fix made to delay the sampling of cmd_in and data_in</td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>GATESDCLKEN</td>
                            <td>RW</td>
                            <td>If this bit is 0, SD_CLK to card will not be gated automatically, when there is no transfer. If this bit set to 1, SD_CLK to card will be gated automatically,when there is no transfer.<br><br>
                                 GATE                 = 0x1 - SD_CLK to card will be gated automatically when there is no transfer.<br>
                             NOGATE               = 0x0 - SD_CLK to card will NOT be gated automatically when there is no transfer.</td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="SLOTSTAT" class="panel-title">SLOTSTAT - Slot interrupt status</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x400700FC</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Slot interrupt status</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="8">VENDORVER
                                <br>0xa</td>

                            <td align="center" colspan="8">SPECVER
                                <br>0x2</td>

                            <td align="center" colspan="8">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="7">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">INTSLOT0
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:24</td>
                            <td>VENDORVER</td>
                            <td>HwInit</td>
                            <td>The Vendor Version Number is set to 0x10 (1.0)<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>23:16</td>
                            <td>SPECVER</td>
                            <td>HwInit</td>
                            <td>The Host Controller Version Number is set to 0x02 (SD Host Specification Version 3.00).<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>15:8</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>7:1</td>
                            <td>RSVD</td>
                            <td>Rsvd</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>INTSLOT0</td>
                            <td>ROC</td>
                            <td>This status bit indicates the OR of Interrupt signal and Wakeup signal for slot<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

    </body>

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            <small>
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